ARM: tegra: clock: Round rate before setting rate

Call the clock's round_rate op, if it exists, before calling
the set_rate op.  This will help later when dvfs is added,
dvfs needs to know what the final rate will be before the
frequency changes.

Also requires fixes to the round rate functions to ensure
calling round rate and then set rate will not cause the
frequency to be rounded down twice.  When picking clock
divider values, the clock framework picks the closest
frequency that is lower than the requested frequency.  If
the new frequency calculated from the divider value is
rounded down, and then passed to set_rate, it will get
rounded down again, possibly resulting in a frequency two
steps lower than the original requested frequency.

Fix the problem by rounding up when calculating the frequency
coming out of a clock divider, so if that frequency is
requested again, the same divider value will be picked.

Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 165aa9c748f6bb419cd0a8d84d50a8970346d1b2..e028320ab423cc4ca7cb1930bc69dd71ee502ed4 100644 (file)
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -86,6 +86,7 @@ static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
 
        if (c->mul != 0 && c->div != 0) {
                rate *= c->mul;
+               rate += c->div - 1; /* round up */
                do_div(rate, c->div);
        }
 
@@ -240,12 +241,23 @@ EXPORT_SYMBOL(clk_get_parent);
 
 int clk_set_rate_locked(struct clk *c, unsigned long rate)
 {
+       long new_rate;
+
        if (!c->ops || !c->ops->set_rate)
                return -ENOSYS;
 
        if (rate > c->max_rate)
                rate = c->max_rate;
 
+       if (c->ops && c->ops->round_rate) {
+               new_rate = c->ops->round_rate(c, rate);
+
+               if (new_rate < 0)
+                       return new_rate;
+
+               rate = new_rate;
+       }
+
        return c->ops->set_rate(c, rate);
 }
 

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 2ca8b74ec07e1cc4c1a3bd1e832b2f6746186f5e..73e112f12695597070a99f1e68b0e6a5bec07013 100644 (file)
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -898,9 +898,9 @@ static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
                divider = clk_div71_get_divider(parent_rate, rate);
                if (divider < 0)
                        return divider;
-               return parent_rate * 2 / (divider + 2);
+               return DIV_ROUND_UP(parent_rate * 2, divider + 2);
        } else if (c->flags & DIV_2) {
-               return parent_rate / 2;
+               return DIV_ROUND_UP(parent_rate, 2);
        }
        return -EINVAL;
 }
@@ -1092,12 +1092,12 @@ static long tegra2_periph_clk_round_rate(struct clk *c,
                if (divider < 0)
                        return divider;
 
-               return parent_rate * 2 / (divider + 2);
+               return DIV_ROUND_UP(parent_rate * 2, divider + 2);
        } else if (c->flags & DIV_U16) {
                divider = clk_div16_get_divider(parent_rate, rate);
                if (divider < 0)
                        return divider;
-               return parent_rate / (divider + 1);
+               return DIV_ROUND_UP(parent_rate, divider + 1);
        }
        return -EINVAL;
 }