drm/exynos: fimd: Add support for FIMD variants with clock selection

Some platforms that can be supported this driver has additional clock
source selection bits in VIDCON0 register that allows to select which
clock should be used to drive the pixel clock: bus clock or special
clock.

Since this driver assumes that special clock always drives the pixel
clock, this patch sets the selection bitfield to use the special clock.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 015a3be0b06ee2673ea5597284a521771e5d4e26..7681a8afa6ed0b66fd33466773e40de0c87d4c77 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -65,6 +65,7 @@ struct fimd_driver_data {
        unsigned int timing_base;
 
        unsigned int has_shadowcon:1;
+       unsigned int has_clksel:1;
 };
 
 static struct fimd_driver_data exynos4_fimd_driver_data = {
@@ -278,6 +279,11 @@ static void fimd_commit(struct device *dev)
        val = ctx->vidcon0;
        val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 
+       if (ctx->driver_data->has_clksel) {
+               val &= ~VIDCON0_CLKSEL_MASK;
+               val |= VIDCON0_CLKSEL_LCD;
+       }
+
        if (ctx->clkdiv > 1)
                val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
        else