}
#endif
+extern void b_sess_control(int val);
int s2mu004_muic_get_vbus_state(struct s2mu004_muic_data *muic_data)
{
struct i2c_client *i2c = muic_data->i2c;
vbus = !!(reg_val & DEV_TYPE_APPLE_VBUS_WAKEUP);
pr_info("%s vbus : (%d)\n", __func__, vbus);
+ if (vbus == 1)
+ b_sess_control(1);
+ else
+ b_sess_control(0);
+
return vbus;
}
return snprintf(buf, PAGE_SIZE, "%d\n", fsm->b_sess_vld);\r
}\r
\r
+struct dwc3 *g_dwc3;\r
+void b_sess_control(int val)\r
+{\r
+ struct dwc3 *dwc = g_dwc3;\r
+ struct otg_fsm *fsm = &dwc->dotg->fsm;\r
+\r
+ fsm->b_sess_vld = !!val;\r
+\r
+ dwc3_otg_run_sm(fsm);\r
+}\r
+EXPORT_SYMBOL_GPL(b_sess_control);\r
+\r
static ssize_t\r
dwc3_otg_store_b_sess(struct device *dev,\r
struct device_attribute *attr, const char *buf, size_t n)\r
struct dwc3_ext_otg_ops *ops = NULL;\r
int ret = 0;\r
\r
+ g_dwc3 = dwc;\r
+\r
dev_info(dwc->dev, "%s\n", __func__);\r
\r
/* EXYNOS SoCs don't have HW OTG, but support SW OTG. */\r