Merge branch 'depends/rmk/restart' into next/cleanup
authorArnd Bergmann <arnd@arndb.de>
Sat, 7 Jan 2012 11:51:28 +0000 (11:51 +0000)
committerArnd Bergmann <arnd@arndb.de>
Sat, 7 Jan 2012 11:51:28 +0000 (11:51 +0000)
Conflicts:
arch/arm/mach-at91/at91cap9.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-exynos/cpu.c
arch/arm/mach-shmobile/board-kota2.c

This resolves a bunch of conflicts between the arm-soc tree
and changes from the arm tree that have gone upstream.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
104 files changed:
1  2 
MAINTAINERS
arch/arm/Kconfig
arch/arm/include/asm/system.h
arch/arm/kernel/perf_event.c
arch/arm/kernel/process.c
arch/arm/kernel/setup.c
arch/arm/mach-at91/at91cap9.c
arch/arm/mach-at91/at91rm9200.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-at91/generic.h
arch/arm/mach-cns3xxx/cns3420vb.c
arch/arm/mach-ep93xx/adssphere.c
arch/arm/mach-ep93xx/edb93xx.c
arch/arm/mach-ep93xx/gesbc9312.c
arch/arm/mach-ep93xx/micro9.c
arch/arm/mach-ep93xx/simone.c
arch/arm/mach-ep93xx/snappercl15.c
arch/arm/mach-ep93xx/ts72xx.c
arch/arm/mach-exynos/common.c
arch/arm/mach-exynos/mach-armlex4210.c
arch/arm/mach-exynos/mach-nuri.c
arch/arm/mach-exynos/mach-origen.c
arch/arm/mach-exynos/mach-smdk4x12.c
arch/arm/mach-exynos/mach-smdkv310.c
arch/arm/mach-exynos/mach-universal_c210.c
arch/arm/mach-highbank/highbank.c
arch/arm/mach-netx/nxdb500.c
arch/arm/mach-netx/nxdkn.c
arch/arm/mach-netx/nxeb500hmi.c
arch/arm/mach-nomadik/board-nhk8815.c
arch/arm/mach-omap2/board-2430sdp.c
arch/arm/mach-omap2/board-3430sdp.c
arch/arm/mach-omap2/board-3630sdp.c
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-am3517crane.c
arch/arm/mach-omap2/board-am3517evm.c
arch/arm/mach-omap2/board-apollon.c
arch/arm/mach-omap2/board-cm-t35.c
arch/arm/mach-omap2/board-cm-t3517.c
arch/arm/mach-omap2/board-devkit8000.c
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/board-h4.c
arch/arm/mach-omap2/board-igep0020.c
arch/arm/mach-omap2/board-ldp.c
arch/arm/mach-omap2/board-n8x0.c
arch/arm/mach-omap2/board-omap3beagle.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/board-omap3logic.c
arch/arm/mach-omap2/board-omap3pandora.c
arch/arm/mach-omap2/board-omap3stalker.c
arch/arm/mach-omap2/board-omap3touchbook.c
arch/arm/mach-omap2/board-omap4panda.c
arch/arm/mach-omap2/board-overo.c
arch/arm/mach-omap2/board-rm680.c
arch/arm/mach-omap2/board-rx51.c
arch/arm/mach-omap2/board-zoom.c
arch/arm/mach-omap2/common.h
arch/arm/mach-realview/realview_eb.c
arch/arm/mach-realview/realview_pb1176.c
arch/arm/mach-realview/realview_pb11mp.c
arch/arm/mach-realview/realview_pba8.c
arch/arm/mach-realview/realview_pbx.c
arch/arm/mach-s3c64xx/mach-anw6410.c
arch/arm/mach-s3c64xx/mach-crag6410.c
arch/arm/mach-s3c64xx/mach-hmt.c
arch/arm/mach-s3c64xx/mach-mini6410.c
arch/arm/mach-s3c64xx/mach-ncp.c
arch/arm/mach-s3c64xx/mach-real6410.c
arch/arm/mach-s3c64xx/mach-smartq5.c
arch/arm/mach-s3c64xx/mach-smartq7.c
arch/arm/mach-s3c64xx/mach-smdk6400.c
arch/arm/mach-s3c64xx/mach-smdk6410.c
arch/arm/mach-s5p64x0/mach-smdk6440.c
arch/arm/mach-s5p64x0/mach-smdk6450.c
arch/arm/mach-s5pc100/mach-smdkc100.c
arch/arm/mach-s5pv210/mach-aquila.c
arch/arm/mach-s5pv210/mach-goni.c
arch/arm/mach-s5pv210/mach-smdkc110.c
arch/arm/mach-s5pv210/mach-smdkv210.c
arch/arm/mach-s5pv210/mach-torbreck.c
arch/arm/mach-shmobile/board-ag5evm.c
arch/arm/mach-shmobile/board-kota2.c
arch/arm/mach-spear3xx/spear300_evb.c
arch/arm/mach-spear3xx/spear310_evb.c
arch/arm/mach-spear3xx/spear320_evb.c
arch/arm/mach-spear6xx/spear600_evb.c
arch/arm/mach-tegra/board-dt.c
arch/arm/mach-tegra/board-harmony.c
arch/arm/mach-tegra/board-paz00.c
arch/arm/mach-tegra/board-seaboard.c
arch/arm/mach-tegra/board-trimslice.c
arch/arm/mach-u300/u300.c
arch/arm/mach-versatile/core.c
arch/arm/mach-versatile/versatile_ab.c
arch/arm/mach-versatile/versatile_dt.c
arch/arm/mach-versatile/versatile_pb.c
arch/arm/mach-vexpress/v2m.c
arch/arm/plat-iop/Makefile
arch/arm/plat-mxc/include/mach/common.h
mm/vmalloc.c

diff --cc MAINTAINERS
Simple merge
Simple merge
Simple merge
Simple merge
index 423bb2019451d2cdc6aa2db543230176bdc08f05,17859ce4e7be3326902b6b828fab9a6ec4d1c190..b29776aa65865dcd621e3707fe7a3b97f37dc61d
@@@ -120,41 -114,11 +120,35 @@@ static void __soft_restart(void *addr
        /* Push out any further dirty data, and ensure cache is empty */
        flush_cache_all();
  
 -      cpu_reset(addr);
 +      /* Switch to the identity mapping. */
 +      phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
 +      phys_reset((unsigned long)addr);
 +
 +      /* Should never get here. */
 +      BUG();
 +}
 +
 +void soft_restart(unsigned long addr)
 +{
 +      u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack);
 +
 +      /* Disable interrupts first */
 +      local_irq_disable();
 +      local_fiq_disable();
 +
 +      /* Disable the L2 if we're the last man standing. */
 +      if (num_online_cpus() == 1)
 +              outer_disable();
 +
 +      /* Change to the new stack and continue with the reset. */
 +      call_with_stack(__soft_restart, (void *)addr, (void *)stack);
 +
 +      /* Should never get here. */
 +      BUG();
  }
  
void arm_machine_restart(char mode, const char *cmd)
static void null_restart(char mode, const char *cmd)
  {
-       /* Disable interrupts first */
-       local_irq_disable();
-       local_fiq_disable();
-       /* Call the architecture specific reboot code. */
-       arch_reset(mode, cmd);
  }
  
  /*
Simple merge
index 506a26c3fff63eeae2673226133489642f64ede9,29373397d2df83c6766a5ee87c098ec55c3892df..edb879ac04c8e30c3d2b814f24497ae86075e7be
@@@ -328,16 -333,10 +328,16 @@@ static void __init at91cap9_map_io(void
        at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
  }
  
 +static void __init at91cap9_ioremap_registers(void)
 +{
 +      at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
 +      at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
 +      at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
 +}
 +
  static void __init at91cap9_initialize(void)
  {
-       at91_arch_reset = at91cap9_reset;
+       arm_pm_restart = at91cap9_restart;
 -      pm_power_off = at91cap9_poweroff;
        at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
  
        /* Register GPIO subsystem */
index 9163d7d5f76e5ff2e7a311994b9da52254ce7961,430a9fdc3dbf5e04662802c17f6cba825d1a16da..99c3174e24a2262d1ff4e5d2cef8a7e54ecef33b
@@@ -308,13 -307,9 +308,13 @@@ static void __init at91rm9200_map_io(vo
        iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
  }
  
 +static void __init at91rm9200_ioremap_registers(void)
 +{
 +}
 +
  static void __init at91rm9200_initialize(void)
  {
-       at91_arch_reset = at91rm9200_reset;
+       arm_pm_restart = at91rm9200_restart;
        at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
                        | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
                        | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
index 3a960d2740b6d111ca4ce341d81fb6cd433d1abe,e76cd49ebc9e8252fc6502c6b071cd4d5a03177c..5e46e4a96430d90e793343115cbce42001e5cecc
@@@ -320,16 -325,10 +320,16 @@@ static void __init at91sam9260_map_io(v
        }
  }
  
 +static void __init at91sam9260_ioremap_registers(void)
 +{
 +      at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
 +      at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
 +      at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 +}
 +
  static void __init at91sam9260_initialize(void)
  {
-       at91_arch_reset = at91sam9_alt_reset;
+       arm_pm_restart = at91sam9_alt_restart;
 -      pm_power_off = at91sam9260_poweroff;
        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                        | (1 << AT91SAM9260_ID_IRQ2);
  
index a0538c5c252029f3c30392eeab9e9608740f767b,19ac7c0729a0bc2d38b1ac9a2dbce81c299f5604..b85b9ea6017071252a670fdb6e22cb222336055d
@@@ -278,16 -285,10 +278,16 @@@ static void __init at91sam9261_map_io(v
                at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
  }
  
 +static void __init at91sam9261_ioremap_registers(void)
 +{
 +      at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
 +      at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
 +      at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 +}
 +
  static void __init at91sam9261_initialize(void)
  {
-       at91_arch_reset = at91sam9_alt_reset;
+       arm_pm_restart = at91sam9_alt_restart;
 -      pm_power_off = at91sam9261_poweroff;
        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                        | (1 << AT91SAM9261_ID_IRQ2);
  
index 5ffbbb024c1e385d2ed966abbb3fc4700d2aeb22,50d016310031aefd557da1323d82549edc9db595..79e3669b1117cbdf7ae18fd685647625766da513
@@@ -298,17 -303,10 +298,17 @@@ static void __init at91sam9263_map_io(v
        at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
  }
  
 +static void __init at91sam9263_ioremap_registers(void)
 +{
 +      at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
 +      at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
 +      at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
 +      at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
 +}
 +
  static void __init at91sam9263_initialize(void)
  {
-       at91_arch_reset = at91sam9_alt_reset;
+       arm_pm_restart = at91sam9_alt_restart;
 -      pm_power_off = at91sam9263_poweroff;
        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
  
        /* Register GPIO subsystem */
index f61eb64e6b3992d1dac8204873374858c0fcba7c,ff21f7a60c63dfa0e32bbfb3e999783109925e9f..7032dd32cdf0fbc207dc265958e70faeb1e32143
@@@ -333,16 -338,10 +333,16 @@@ static void __init at91sam9g45_map_io(v
        init_consistent_dma_size(SZ_4M);
  }
  
 +static void __init at91sam9g45_ioremap_registers(void)
 +{
 +      at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
 +      at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
 +      at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
 +}
 +
  static void __init at91sam9g45_initialize(void)
  {
-       at91_arch_reset = at91sam9g45_reset;
+       arm_pm_restart = at91sam9g45_restart;
 -      pm_power_off = at91sam9g45_poweroff;
        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
  
        /* Register GPIO subsystem */
index 96247f68b9d242745645c8a6b1acde694f1078b5,61cbb46f5b0eed6b8bd5a8269efa657696b1e3c2..d6bcb1da11dfbc004d0c59890d60fef8d3dde27f
@@@ -283,16 -290,10 +283,16 @@@ static void __init at91sam9rl_map_io(vo
        at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
  }
  
 +static void __init at91sam9rl_ioremap_registers(void)
 +{
 +      at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
 +      at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
 +      at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
 +}
 +
  static void __init at91sam9rl_initialize(void)
  {
-       at91_arch_reset = at91sam9_alt_reset;
+       arm_pm_restart = at91sam9_alt_restart;
 -      pm_power_off = at91sam9rl_poweroff;
        at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
  
        /* Register GPIO subsystem */
index 40309588f3600a0ce0c779e50b2fba4f1d3b788a,7f4503bc4cbb10f89da3b3bf025829ebaa9319b5..4866b8180d66610d17d6a0576424e19a751995a0
@@@ -58,11 -57,8 +58,11 @@@ extern void at91_irq_suspend(void)
  extern void at91_irq_resume(void);
  
  /* reset */
- extern void at91sam9_alt_reset(void);
+ extern void at91sam9_alt_restart(char, const char *);
  
 +/* shutdown */
 +extern void at91_ioremap_shdwc(u32 base_addr);
 +
   /* GPIO */
  #define AT91RM9200_PQFP               3       /* AT91RM9200 PQFP package has 3 banks */
  #define AT91RM9200_BGA                4       /* AT91RM9200 BGA package has 4 banks */
index 594852fe24cc1dfe517e904e383cc677c73a819e,9b8c3d59731bf625670b2e4737d2e3d01c177847..2c5fb4c7e509b8786fb1ba0d45cb974bc373f4d2
@@@ -202,6 -201,6 +202,7 @@@ MACHINE_START(CNS3420VB, "Cavium Networ
        .map_io         = cns3420_map_io,
        .init_irq       = cns3xxx_init_irq,
        .timer          = &cns3xxx_timer,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = cns3420_init,
+       .restart        = cns3xxx_restart,
  MACHINE_END
index d9b0ea2ba4d80c6769fe6b822c759307a2bd1585,7b41651728cdf406efd2becb71124653a614c86d..681e939407d4bc907dfb99f528992c12bb462eec
@@@ -37,7 -36,7 +37,8 @@@ MACHINE_START(ADSSPHERE, "ADS Sphere bo
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = adssphere_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
index 9bbae0835f27925037498db672836100d2490c60,c5731c68acc02b69199a56a89b4724177465f68f..d115653edca3e3cd9632fcfb14ebb616dad7a985
@@@ -251,9 -250,9 +251,10 @@@ MACHINE_START(EDB9301, "Cirrus Logic ED
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -263,9 -262,9 +264,10 @@@ MACHINE_START(EDB9302, "Cirrus Logic ED
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -275,9 -274,9 +277,10 @@@ MACHINE_START(EDB9302A, "Cirrus Logic E
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -287,9 -286,9 +290,10 @@@ MACHINE_START(EDB9307, "Cirrus Logic ED
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -299,9 -298,9 +303,10 @@@ MACHINE_START(EDB9307A, "Cirrus Logic E
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -311,9 -310,9 +316,10 @@@ MACHINE_START(EDB9312, "Cirrus Logic ED
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -323,9 -322,9 +329,10 @@@ MACHINE_START(EDB9315, "Cirrus Logic ED
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -335,8 -334,8 +342,9 @@@ MACHINE_START(EDB9315A, "Cirrus Logic E
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
index 1dd32a7c5f151767037a6f365232589ec1d909ca,7b89e8a1bb7b9ad7c1bb8d01f77eb9cda14171e1..af46970dc58e78c2a484c4db0351c1eb8f94ab4b
@@@ -37,7 -36,7 +37,8 @@@ MACHINE_START(GESBC9312, "Glomation GES
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = gesbc9312_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
index a6dae6c2e3c1f96b749eb8526fccfbd7cf4b04d7,050ce9216d7cb1c7373ec452d10eb11c6628c2b4..7b98084f0c97bf14e8830a30b3dd18b10d5a3163
@@@ -81,9 -80,9 +81,10 @@@ MACHINE_START(MICRO9, "Contec Micro9-Hi
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -93,9 -92,9 +94,10 @@@ MACHINE_START(MICRO9M, "Contec Micro9-M
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -105,9 -104,9 +107,10 @@@ MACHINE_START(MICRO9L, "Contec Micro9-L
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
  
@@@ -117,8 -116,8 +120,9 @@@ MACHINE_START(MICRO9S, "Contec Micro9-S
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
  #endif
index 40121ba8e711f76359d8017ded27d127aa1843b1,188cbdb4dbdadf6101e26f2262507650eeb280b2..f4e553eca21c7d7c4cfdfd406489a34623945592
@@@ -81,7 -80,7 +81,8 @@@ MACHINE_START(SIM_ONE, "Simplemachines 
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = simone_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
index ec7c63ff01e22e4e62f7e678069778bcd828fac9,797afdee80abd7fa2f06aefddade9e938a14dafa..fd846331ddff9119023c2a726adae50a16578f6f
@@@ -178,7 -177,7 +178,8 @@@ MACHINE_START(SNAPPER_CL15, "Bluewater 
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = snappercl15_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
index 760384e6407de90adc04fd78781df2ef2ba7da67,de9bb541b5500a35992d818692d01cfd47a192ed..79f8ecf07a190a082ac4da524ef185faea62715a
@@@ -248,7 -247,7 +248,8 @@@ MACHINE_START(TS72XX, "Technologic Syst
        .atag_offset    = 0x100,
        .map_io         = ts72xx_map_io,
        .init_irq       = ep93xx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = ts72xx_init_machine,
+       .restart        = ep93xx_restart,
  MACHINE_END
index 0000000000000000000000000000000000000000,6f567a4d85190791fa21cf712621ef81681b7479..5de4214fa78ff9fe26f3acb9cdf4c263d9cbc9a3
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,718 +1,704 @@@
 -unsigned int gic_bank_offset __read_mostly;
 -
+ /*
+  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+  *            http://www.samsung.com
+  *
+  * Common Codes for EXYNOS
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
+ #include <linux/kernel.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+ #include <linux/io.h>
+ #include <linux/sysdev.h>
+ #include <linux/gpio.h>
+ #include <linux/sched.h>
+ #include <linux/serial_core.h>
+ #include <asm/proc-fns.h>
++#include <asm/exception.h>
+ #include <asm/hardware/cache-l2x0.h>
+ #include <asm/hardware/gic.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/irq.h>
+ #include <mach/regs-irq.h>
+ #include <mach/regs-pmu.h>
+ #include <mach/regs-gpio.h>
+ #include <plat/cpu.h>
+ #include <plat/clock.h>
+ #include <plat/devs.h>
+ #include <plat/pm.h>
+ #include <plat/sdhci.h>
+ #include <plat/gpio-cfg.h>
+ #include <plat/adc-core.h>
+ #include <plat/fb-core.h>
+ #include <plat/fimc-core.h>
+ #include <plat/iic-core.h>
+ #include <plat/tv-core.h>
+ #include <plat/regs-serial.h>
+ #include "common.h"
 -static void exynos4_gic_irq_fix_base(struct irq_data *d)
 -{
 -      struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 -
 -      gic_data->cpu_base = S5P_VA_GIC_CPU +
 -                          (gic_bank_offset * smp_processor_id());
 -
 -      gic_data->dist_base = S5P_VA_GIC_DIST +
 -                          (gic_bank_offset * smp_processor_id());
 -}
 -
+ static const char name_exynos4210[] = "EXYNOS4210";
+ static const char name_exynos4212[] = "EXYNOS4212";
+ static const char name_exynos4412[] = "EXYNOS4412";
+ static struct cpu_table cpu_ids[] __initdata = {
+       {
+               .idcode         = EXYNOS4210_CPU_ID,
+               .idmask         = EXYNOS4_CPU_MASK,
+               .map_io         = exynos4_map_io,
+               .init_clocks    = exynos4_init_clocks,
+               .init_uarts     = exynos4_init_uarts,
+               .init           = exynos_init,
+               .name           = name_exynos4210,
+       }, {
+               .idcode         = EXYNOS4212_CPU_ID,
+               .idmask         = EXYNOS4_CPU_MASK,
+               .map_io         = exynos4_map_io,
+               .init_clocks    = exynos4_init_clocks,
+               .init_uarts     = exynos4_init_uarts,
+               .init           = exynos_init,
+               .name           = name_exynos4212,
+       }, {
+               .idcode         = EXYNOS4412_CPU_ID,
+               .idmask         = EXYNOS4_CPU_MASK,
+               .map_io         = exynos4_map_io,
+               .init_clocks    = exynos4_init_clocks,
+               .init_uarts     = exynos4_init_uarts,
+               .init           = exynos_init,
+               .name           = name_exynos4412,
+       },
+ };
+ /* Initial IO mappings */
+ static struct map_desc exynos_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_CHIPID,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_SYS,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_TIMER,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_PMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
+               .length         = SZ_512K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
+               .length         = SZ_128K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
+               .length         = SZ_8K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_L2CC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO1,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO2,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO3,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
+               .length         = SZ_256,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_DMC0,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc0[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc1[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static void exynos_idle(void)
+ {
+       if (!need_resched())
+               cpu_do_idle();
+       local_irq_enable();
+ }
+ void exynos4_restart(char mode, const char *cmd)
+ {
+       __raw_writel(0x1, S5P_SWRESET);
+ }
+ /*
+  * exynos_map_io
+  *
+  * register the standard cpu IO areas
+  */
+ void __init exynos_init_io(struct map_desc *mach_desc, int size)
+ {
+       /* initialize the io descriptors we need for initialization */
+       iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+       if (mach_desc)
+               iotable_init(mach_desc, size);
+       /* detect cpu id and rev. */
+       s5p_init_cpu(S5P_VA_CHIPID);
+       s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+ }
+ void __init exynos4_map_io(void)
+ {
+       iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+       if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+               iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
+       else
+               iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
+       /* initialize device information early */
+       exynos4_default_sdhci0();
+       exynos4_default_sdhci1();
+       exynos4_default_sdhci2();
+       exynos4_default_sdhci3();
+       s3c_adc_setname("samsung-adc-v3");
+       s3c_fimc_setname(0, "exynos4-fimc");
+       s3c_fimc_setname(1, "exynos4-fimc");
+       s3c_fimc_setname(2, "exynos4-fimc");
+       s3c_fimc_setname(3, "exynos4-fimc");
+       /* The I2C bus controllers are directly compatible with s3c2440 */
+       s3c_i2c0_setname("s3c2440-i2c");
+       s3c_i2c1_setname("s3c2440-i2c");
+       s3c_i2c2_setname("s3c2440-i2c");
+       s5p_fb_setname(0, "exynos4-fb");
+       s5p_hdmi_setname("exynos4-hdmi");
+ }
+ void __init exynos4_init_clocks(int xtal)
+ {
+       printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+       s3c24xx_register_baseclocks(xtal);
+       s5p_register_clocks(xtal);
+       if (soc_is_exynos4210())
+               exynos4210_register_clocks();
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               exynos4212_register_clocks();
+       exynos4_register_clocks();
+       exynos4_setup_clocks();
+ }
+ #define COMBINER_ENABLE_SET   0x0
+ #define COMBINER_ENABLE_CLEAR 0x4
+ #define COMBINER_INT_STATUS   0xC
+ static DEFINE_SPINLOCK(irq_controller_lock);
+ struct combiner_chip_data {
+       unsigned int irq_offset;
+       unsigned int irq_mask;
+       void __iomem *base;
+ };
+ static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
+ static inline void __iomem *combiner_base(struct irq_data *data)
+ {
+       struct combiner_chip_data *combiner_data =
+               irq_data_get_irq_chip_data(data);
+       return combiner_data->base;
+ }
+ static void combiner_mask_irq(struct irq_data *data)
+ {
+       u32 mask = 1 << (data->irq % 32);
+       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+ }
+ static void combiner_unmask_irq(struct irq_data *data)
+ {
+       u32 mask = 1 << (data->irq % 32);
+       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+ }
+ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+ {
+       struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+       unsigned int cascade_irq, combiner_irq;
+       unsigned long status;
+       chained_irq_enter(chip, desc);
+       spin_lock(&irq_controller_lock);
+       status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+       spin_unlock(&irq_controller_lock);
+       status &= chip_data->irq_mask;
+       if (status == 0)
+               goto out;
+       combiner_irq = __ffs(status);
+       cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
+       if (unlikely(cascade_irq >= NR_IRQS))
+               do_bad_IRQ(cascade_irq, desc);
+       else
+               generic_handle_irq(cascade_irq);
+  out:
+       chained_irq_exit(chip, desc);
+ }
+ static struct irq_chip combiner_chip = {
+       .name           = "COMBINER",
+       .irq_mask       = combiner_mask_irq,
+       .irq_unmask     = combiner_unmask_irq,
+ };
+ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
+ {
+       if (combiner_nr >= MAX_COMBINER_NR)
+               BUG();
+       if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
+               BUG();
+       irq_set_chained_handler(irq, combiner_handle_cascade_irq);
+ }
+ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
+                         unsigned int irq_start)
+ {
+       unsigned int i;
+       if (combiner_nr >= MAX_COMBINER_NR)
+               BUG();
+       combiner_data[combiner_nr].base = base;
+       combiner_data[combiner_nr].irq_offset = irq_start;
+       combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+       /* Disable all interrupts */
+       __raw_writel(combiner_data[combiner_nr].irq_mask,
+                    base + COMBINER_ENABLE_CLEAR);
+       /* Setup the Linux IRQ subsystem */
+       for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+                               + MAX_IRQ_IN_COMBINER; i++) {
+               irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
+               irq_set_chip_data(i, &combiner_data[combiner_nr]);
+               set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+       }
+ }
 -      gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 -      gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
 -      gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
 -      gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
+ void __init exynos4_init_irq(void)
+ {
+       int irq;
++      unsigned int gic_bank_offset;
+       gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
++      gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
+       for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+               combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+                               COMBINER_IRQ(irq, 0));
+               combiner_cascade_irq(irq, IRQ_SPI(irq));
+       }
+       /*
+        * The parameters of s5p_init_irq() are for VIC init.
+        * Theses parameters should be NULL and 0 because EXYNOS4
+        * uses GIC instead of VIC.
+        */
+       s5p_init_irq(NULL, 0);
+ }
+ struct sysdev_class exynos4_sysclass = {
+       .name   = "exynos4-core",
+ };
+ static struct sys_device exynos4_sysdev = {
+       .cls    = &exynos4_sysclass,
+ };
+ static int __init exynos4_core_init(void)
+ {
+       return sysdev_class_register(&exynos4_sysclass);
+ }
+ core_initcall(exynos4_core_init);
+ #ifdef CONFIG_CACHE_L2X0
+ static int __init exynos4_l2x0_cache_init(void)
+ {
+       /* TAG, Data Latency Control: 2cycle */
+       __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+       if (soc_is_exynos4210())
+               __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+       /* L2X0 Prefetch Control */
+       __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+       /* L2X0 Power Control */
+       __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+                    S5P_VA_L2CC + L2X0_POWER_CTRL);
+       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
+       return 0;
+ }
+ early_initcall(exynos4_l2x0_cache_init);
+ #endif
+ int __init exynos_init(void)
+ {
+       printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+       /* set idle function */
+       pm_idle = exynos_idle;
+       return sysdev_register(&exynos4_sysdev);
+ }
+ static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
+       [0] = {
+               .name           = "uclk1",
+               .divisor        = 1,
+               .min_baud       = 0,
+               .max_baud       = 0,
+       },
+ };
+ /* uart registration process */
+ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+ {
+       struct s3c2410_uartcfg *tcfg = cfg;
+       u32 ucnt;
+       for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
+               if (!tcfg->clocks) {
+                       tcfg->has_fracval = 1;
+                       tcfg->clocks = exynos4_serial_clocks;
+                       tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
+               }
+               tcfg->flags |= NO_NEED_CHECK_CLKSRC;
+       }
+       s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
+ }
+ static DEFINE_SPINLOCK(eint_lock);
+ static unsigned int eint0_15_data[16];
+ static unsigned int exynos4_get_irq_nr(unsigned int number)
+ {
+       u32 ret = 0;
+       switch (number) {
+       case 0 ... 3:
+               ret = (number + IRQ_EINT0);
+               break;
+       case 4 ... 7:
+               ret = (number + (IRQ_EINT4 - 4));
+               break;
+       case 8 ... 15:
+               ret = (number + (IRQ_EINT8 - 8));
+               break;
+       default:
+               printk(KERN_ERR "number available : %d\n", number);
+       }
+       return ret;
+ }
+ static inline void exynos4_irq_eint_mask(struct irq_data *data)
+ {
+       u32 mask;
+       spin_lock(&eint_lock);
+       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask |= eint_irq_to_bit(data->irq);
+       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+ }
+ static void exynos4_irq_eint_unmask(struct irq_data *data)
+ {
+       u32 mask;
+       spin_lock(&eint_lock);
+       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask &= ~(eint_irq_to_bit(data->irq));
+       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+ }
+ static inline void exynos4_irq_eint_ack(struct irq_data *data)
+ {
+       __raw_writel(eint_irq_to_bit(data->irq),
+                    S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+ }
+ static void exynos4_irq_eint_maskack(struct irq_data *data)
+ {
+       exynos4_irq_eint_mask(data);
+       exynos4_irq_eint_ack(data);
+ }
+ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+ {
+       int offs = EINT_OFFSET(data->irq);
+       int shift;
+       u32 ctrl, mask;
+       u32 newvalue = 0;
+       switch (type) {
+       case IRQ_TYPE_EDGE_RISING:
+               newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+               break;
+       case IRQ_TYPE_EDGE_FALLING:
+               newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+               break;
+       case IRQ_TYPE_EDGE_BOTH:
+               newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+               break;
+       case IRQ_TYPE_LEVEL_LOW:
+               newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+               break;
+       case IRQ_TYPE_LEVEL_HIGH:
+               newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+               break;
+       default:
+               printk(KERN_ERR "No such irq type %d", type);
+               return -EINVAL;
+       }
+       shift = (offs & 0x7) * 4;
+       mask = 0x7 << shift;
+       spin_lock(&eint_lock);
+       ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       ctrl &= ~mask;
+       ctrl |= newvalue << shift;
+       __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+       switch (offs) {
+       case 0 ... 7:
+               s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+               break;
+       case 8 ... 15:
+               s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+               break;
+       case 16 ... 23:
+               s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+               break;
+       case 24 ... 31:
+               s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+               break;
+       default:
+               printk(KERN_ERR "No such irq number %d", offs);
+       }
+       return 0;
+ }
+ static struct irq_chip exynos4_irq_eint = {
+       .name           = "exynos4-eint",
+       .irq_mask       = exynos4_irq_eint_mask,
+       .irq_unmask     = exynos4_irq_eint_unmask,
+       .irq_mask_ack   = exynos4_irq_eint_maskack,
+       .irq_ack        = exynos4_irq_eint_ack,
+       .irq_set_type   = exynos4_irq_eint_set_type,
+ #ifdef CONFIG_PM
+       .irq_set_wake   = s3c_irqext_wake,
+ #endif
+ };
+ /*
+  * exynos4_irq_demux_eint
+  *
+  * This function demuxes the IRQ from from EINTs 16 to 31.
+  * It is designed to be inlined into the specific handler
+  * s5p_irq_demux_eintX_Y.
+  *
+  * Each EINT pend/mask registers handle eight of them.
+  */
+ static inline void exynos4_irq_demux_eint(unsigned int start)
+ {
+       unsigned int irq;
+       u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+       u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+       status &= ~mask;
+       status &= 0xff;
+       while (status) {
+               irq = fls(status) - 1;
+               generic_handle_irq(irq + start);
+               status &= ~(1 << irq);
+       }
+ }
+ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+ {
+       struct irq_chip *chip = irq_get_chip(irq);
+       chained_irq_enter(chip, desc);
+       exynos4_irq_demux_eint(IRQ_EINT(16));
+       exynos4_irq_demux_eint(IRQ_EINT(24));
+       chained_irq_exit(chip, desc);
+ }
+ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+ {
+       u32 *irq_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+       chained_irq_enter(chip, desc);
+       chip->irq_mask(&desc->irq_data);
+       if (chip->irq_ack)
+               chip->irq_ack(&desc->irq_data);
+       generic_handle_irq(*irq_data);
+       chip->irq_unmask(&desc->irq_data);
+       chained_irq_exit(chip, desc);
+ }
+ int __init exynos4_init_irq_eint(void)
+ {
+       int irq;
+       for (irq = 0 ; irq <= 31 ; irq++) {
+               irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+                                        handle_level_irq);
+               set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+       }
+       irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+       for (irq = 0 ; irq <= 15 ; irq++) {
+               eint0_15_data[irq] = IRQ_EINT(irq);
+               irq_set_handler_data(exynos4_get_irq_nr(irq),
+                                    &eint0_15_data[irq]);
+               irq_set_chained_handler(exynos4_get_irq_nr(irq),
+                                       exynos4_irq_eint0_15);
+       }
+       return 0;
+ }
+ arch_initcall(exynos4_init_irq_eint);
index 49da3089249a04244f4df5e592ded614a694ee65,9a2b99646d267cb857d0bdb3556c4743dfbb474d..d726fcd3acf99204b58cfc6fe49a6633ff7b4b9e
@@@ -211,7 -211,7 +212,8 @@@ MACHINE_START(ARMLEX4210, "ARMLEX4210"
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = armlex4210_map_io,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = armlex4210_machine_init,
        .timer          = &exynos4_timer,
+       .restart        = exynos4_restart,
  MACHINE_END
Simple merge
Simple merge
index 722d82d7f217dca6c748616ce6e9f735f70a113b,375b5aa5e163828202cbfb70da5a8c6ab9bde2b7..d00e4f016a684c5c37715c46618e303661e115bd
@@@ -288,9 -288,9 +289,10 @@@ MACHINE_START(SMDK4212, "SMDK4212"
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
+       .restart        = exynos4_restart,
  MACHINE_END
  
  MACHINE_START(SMDK4412, "SMDK4412")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
+       .restart        = exynos4_restart,
  MACHINE_END
index edc60b6108ed301c05beff160b81fc5051a22363,f2552ff5ddb018b7a192a7bf2f6ddeb97d4fbff9..5b365613b470531977e62e774a027e0854750f44
@@@ -387,7 -387,7 +389,8 @@@ MACHINE_START(SMDKC210, "SMDKC210"
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = smdkv310_machine_init,
        .timer          = &exynos4_timer,
+       .restart        = exynos4_restart,
  MACHINE_END
index 7266dd510f1a4ed9dd495c3268f6430a776b3dc4,4508384f100fdcab8e6e2aed8d453fbef7d12a69..804c4a55f8038c75cbf0731168ee6d0d36de004a
@@@ -144,7 -144,7 +144,8 @@@ DT_MACHINE_START(HIGHBANK, "Highbank"
        .map_io         = highbank_map_io,
        .init_irq       = highbank_init_irq,
        .timer          = &highbank_timer,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = highbank_init,
        .dt_compat      = highbank_match,
+       .restart        = highbank_restart,
  MACHINE_END
index ef8cf3574a0259756ac89284bb74eff300757c36,5384b5a78f688bcb9a976957c9bae392ffac6b02..180ea899a48afcf76586f24cf1a68cca5438f098
@@@ -204,7 -203,7 +204,8 @@@ MACHINE_START(NXDB500, "Hilscher nxdb50
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxdb500_init,
+       .restart        = netx_restart,
  MACHINE_END
index 588558bdd800c160429300220e69ddcc16d69cc3,2df3783ef45933fd56c39dbe269caf985dbe6497..58009e29b20e722d5f9759d148d3a26e1b3fbcc4
@@@ -97,7 -96,7 +97,8 @@@ MACHINE_START(NXDKN, "Hilscher nxdkn"
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxdkn_init,
+       .restart        = netx_restart,
  MACHINE_END
index cfcbb50386487f450ed3de4546327df2980a4349,26255b2ce47386a544a7c983e22b3ba2176c6f13..122e99826ef6fd0869a80f2935352c081a000ec1
@@@ -181,7 -180,7 +181,8 @@@ MACHINE_START(NXEB500HMI, "Hilscher nxe
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxeb500hmi_init,
+       .restart        = netx_restart,
  MACHINE_END
index f98259c050eea48acd4b480ba1058ed339ed656c,68c7b79bad790f2f5a134c1a958255cb3baf5a00..7c878bf0034094fbbc8e31a933f9d091b4ae95f0
@@@ -281,7 -282,7 +283,8 @@@ MACHINE_START(NOMADIK, "NHK8815"
        .atag_offset    = 0x100,
        .map_io         = cpu8815_map_io,
        .init_irq       = cpu8815_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &nomadik_timer,
        .init_machine   = nhk8815_platform_init,
+       .restart        = cpu8815_restart,
  MACHINE_END
index d88143faca59c33d0d277c33a01954c40d75b473,2e730242132f31d8404f18463e4290a705c1d061..7370983f809fc3994a8722970f2c6f7f1a85f08e
@@@ -301,7 -301,7 +301,8 @@@ MACHINE_START(OMAP_2430SDP, "OMAP2430 s
        .map_io         = omap243x_map_io,
        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
 +      .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_2430sdp_init,
        .timer          = &omap2_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 83126368ed99f2bf0d32679c0ec1e2cb265a5516,7111677c7e6b7bf64cc1d1aedb09fa0ebbef7fb7..9996334cb6879f2fe6b7b770608a7db7cde8375f
@@@ -728,7 -728,7 +728,8 @@@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_3430sdp_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 7969dd904bd3a5ae9f3bca43cf8911018c1c965a,a01d08118a405d5121ec3c4caedd1dfcadadc26c..6ef350d1ae4f40a89a8b1bc54c6858780db1b2a8
@@@ -215,7 -215,7 +215,8 @@@ MACHINE_START(OMAP_3630SDP, "OMAP 3630S
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_sdp_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index ef2bbc09428a2e29b2786bbeb623ac307e1d1ed8,8a46ad8f1227de145c960f633f203c0923de65c3..bad5d5a5ef7949fafdeb06ce4a2e95d686eeb29c
@@@ -984,7 -983,7 +984,8 @@@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = omap_4430sdp_init,
        .timer          = &omap4_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 7e90f93263dba49e0470915b16cacaf0fe6b0e08,c1d6b6338b005ef0f09027997d8752f9f53e0e33..c3851e8de28bf78d94f4be19baa0ca869915cd95
@@@ -98,7 -98,7 +98,8 @@@ MACHINE_START(CRANEBOARD, "AM3517/05 CR
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_crane_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 551cae8d9b8a08b036a135bc7be1f72176adbd75,18c079070ec3ecda655f6b096d4d8db5ceaf92ea..f5a3a3f117394e0c713b9deff1419f9f02fba415
@@@ -491,7 -491,7 +491,8 @@@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_evm_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 5a66480feed099f0463209c05f194b280a69f5ac,75c731c45b2df364c7fb88e4cd5e319ed226de96..ac773829941f487493f4ce0592dfa787592211a9
@@@ -354,7 -354,7 +354,8 @@@ MACHINE_START(OMAP_APOLLON, "OMAP24xx A
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
 +      .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_apollon_init,
        .timer          = &omap2_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 510b6a2ff0fa3c3675d81f54374e58bc89d41e62,c3402cdf0bac212b63dff4c87897b5f0c165ada3..1545102d1f9b2b5a8471785aadfe463f84185d30
@@@ -634,9 -634,9 +634,10 @@@ MACHINE_START(CM_T35, "Compulab CM-T35"
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t35_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
  
  MACHINE_START(CM_T3730, "Compulab CM-T3730")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3730_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index efc5cedb1fbb86f51c20aeacaf5775eea772bd27,0b06ac3d440b4c8c55c7046c266b7fcaf8f91c11..f36d694d21590e069aa390a66eb56024d113d8f7
@@@ -299,7 -299,7 +299,8 @@@ MACHINE_START(CM_T3517, "Compulab CM-T3
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3517_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index d81ea7fa75ef6f59425d1f44c05af46a6ea339d0,519e5f9d491cb30d43c467c1d6ed7f590c8f97f0..e873063f4fdaf4cac7fffe5d18ca718a79cb84fe
@@@ -660,7 -660,7 +660,8 @@@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = devkit8000_init,
        .timer          = &omap3_secure_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
Simple merge
index ec4018362e8ea3f9e8a1d937e9ca0b2f92ccaf59,34ccde484fa61eed35644ecc193d984df59b692c..54af800d143c0e261b4acd6548103c6b3c08634f
@@@ -396,7 -396,7 +396,8 @@@ MACHINE_START(OMAP_H4, "OMAP2420 H4 boa
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
 +      .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_h4_init,
        .timer          = &omap2_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 5949f6ae3edf6038cdf1c4d46798924e09da2b92,e1850d555616bd2ebaa7e0e3ae834d7b9b5566ad..a59ace0ed560a57cdf1009cd15d596b94d71c76d
@@@ -672,9 -672,9 +672,10 @@@ MACHINE_START(IGEP0020, "IGEP v2 board"
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
  
  MACHINE_START(IGEP0030, "IGEP OMAP3 module")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 13bde0e6693463a61610eba0749ad2315571e119,84bbdd6e5aff7c0b8628446f6feac9736b0567c1..2d2a61f7dcbf8e3d799fee8054a39011d94ab603
@@@ -434,7 -434,7 +434,8 @@@ MACHINE_START(OMAP_LDP, "OMAP LDP board
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_ldp_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index bebd3d84365eec43e34eb5f786b1956c27e0a15b,cc1dd541224a8fb096862f5a62a8a77ab6c5244c..cef2cf1c0b8d9affe9afdedcaa16376b1caab783
@@@ -689,9 -689,9 +689,10 @@@ MACHINE_START(NOKIA_N800, "Nokia N800"
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
 +      .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
  
  MACHINE_START(NOKIA_N810, "Nokia N810")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
 +      .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
  
  MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
 +      .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index c34f56588284bfe00deff8c0ca6d19d36245395d,bb6031f6dcb6f4ebf12d8f4bd71f684adc25c226..7ffcd2839e7ba872d872e0a53476b2e95832c2a2
@@@ -559,7 -559,7 +559,8 @@@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beag
        .map_io         = omap3_map_io,
        .init_early     = omap3_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_beagle_init,
        .timer          = &omap3_secure_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index f11bc444e7befeddacc57b6f24ceef9fff5f446f,60912e4732531961913e2430c85581dd19d31d1c..003fe34c934311251452ba4af1efc20382dbbdb6
@@@ -681,7 -681,7 +681,8 @@@ MACHINE_START(OMAP3EVM, "OMAP3 EVM"
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_evm_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 5fa6bad9574ee812aeed2579e42c40942600b1eb,7ecf04a3ff1db63c5bbce743ad1e29c5512dfcf4..4198dd017d8fdfde7fd00b2a8a00d5f9d7e766fb
@@@ -208,9 -208,9 +208,10 @@@ MACHINE_START(OMAP3_TORPEDO, "Logic OMA
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
  
  MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index ef315c585b752e7c0c845fac37bd6dbbb8bc52de,7071a2473a6b0cbdd5eb83c04a4b63efa1eeee53..1644b73017fcafbdc0e7b87a503ac35f92e8f992
@@@ -606,7 -606,7 +606,8 @@@ MACHINE_START(OMAP3_PANDORA, "Pandora H
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3pandora_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index b21d70a2e4a7229efae9a754bb1ab37f63438efe,6e47987d989b98c4b0de9cf8ec2e8a728d549615..cb089a46f62f691cceec4c20f9f035111dded5a3
@@@ -454,7 -454,7 +454,8 @@@ MACHINE_START(SBC3530, "OMAP3 STALKER"
        .map_io                 = omap3_map_io,
        .init_early             = omap35xx_init_early,
        .init_irq               = omap3_init_irq,
 +      .handle_irq             = omap3_intc_handle_irq,
        .init_machine           = omap3_stalker_init,
        .timer                  = &omap3_secure_timer,
+       .restart                = omap_prcm_restart,
  MACHINE_END
index 18cd340f9b7bfb232937404167ed53993676de89,5bb590a40f2bbed16c6c67ab641b5dc07ba73486..a0b851aafccad1bc87d900d9474cfa689e8cf39d
@@@ -381,7 -381,7 +381,8 @@@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbo
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_touchbook_init,
        .timer          = &omap3_secure_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index b6f114436dbc74bb93d09300deef50db59b57c52,955cbee91b4624044245beaa6f39920b7c7e24e3..8b06c6a60d02767819f4cdb833f72f3f6471c580
@@@ -577,7 -576,7 +577,8 @@@ MACHINE_START(OMAP4_PANDA, "OMAP4 Pand
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = omap4_panda_init,
        .timer          = &omap4_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 60a61ea759bf4262b3fd7e529650bf91a0118157,c14d78129999a764fcae3c64c42860e208540e0e..52c0cef77165cb2cbc8a658d8fd63b260ec5662a
@@@ -562,7 -562,7 +562,8 @@@ MACHINE_START(OVERO, "Gumstix Overo"
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = overo_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index a79d49e3fe09a2442ee59debb5ace8480a677a6c,0c67ecc244d688dc255c86fd2bc3f3db0dcecf0b..8678b386c6a2ab8e7a0b664546f837eb9966d36f
@@@ -149,7 -149,7 +149,8 @@@ MACHINE_START(NOKIA_RM680, "Nokia RM-68
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rm680_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 4e3c0965edf3d0a39df68505d3bc3cd30af721ea,c3e716ad2b513bd34ad1b3d3d535c4477f9aafa6..27f01f051dfff07135762b216621eabbc6bf1046
@@@ -127,7 -127,7 +127,8 @@@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rx51_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
index 70e5b54a2115ec3adfbaa6746e619f28ccb8655a,68d6f1c875b816f41739d94c538150f52e03692d..5c20bcc57f2b951d50fe2bef11080b36e9729a36
@@@ -135,9 -135,9 +135,10 @@@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 b
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
  
  MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
 +      .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
+       .restart        = omap_prcm_restart,
  MACHINE_END
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 202c3c6ec9d8667759a22bd6079835be18220a3f,7119b87cbfa0caa2727334b7815a8cf388ff6077..f71fa3c13c8c1a4e3c77f6802014fca113b3a5a4
@@@ -607,8 -607,9 +607,9 @@@ struct sys_timer ag5evm_timer = 
  
  MACHINE_START(AG5EVM, "ag5evm")
        .map_io         = ag5evm_map_io,
+       .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
 -      .handle_irq     = shmobile_handle_irq_gic,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = ag5evm_init,
        .timer          = &ag5evm_timer,
  MACHINE_END
index 1b4439d3f9d51e41b9c3c0824eb5990389cd1343,f44150b5ae46fc3a9f9c7ef57d04a30b2031dde3..857ceeec1bb0e9975eb589deb82fbde7a9be856a
@@@ -447,8 -549,9 +549,9 @@@ struct sys_timer kota2_timer = 
  
  MACHINE_START(KOTA2, "kota2")
        .map_io         = kota2_map_io,
-       .init_irq       = kota2_init_irq,
+       .nr_irqs        = NR_IRQS_LEGACY,
+       .init_irq       = sh73a0_init_irq,
 -      .handle_irq     = shmobile_handle_irq_gic,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = kota2_init,
        .timer          = &kota2_timer,
  MACHINE_END
index 61068ba67923536ce8604b96cc4a4b1d595bdd16,8b429f05b6133612e7ce43467392810674587a6a..3462ab9d612231b5107cad2787ffd67c7fdc2632
@@@ -68,7 -67,7 +68,8 @@@ MACHINE_START(SPEAR300, "ST-SPEAR300-EV
        .atag_offset    =       0x100,
        .map_io         =       spear3xx_map_io,
        .init_irq       =       spear3xx_init_irq,
 +      .handle_irq     =       vic_handle_irq,
        .timer          =       &spear3xx_timer,
        .init_machine   =       spear300_evb_init,
+       .restart        =       spear_restart,
  MACHINE_END
index 7903abe92bf6f9c6c2029c6693c5789f5b0698cd,a11d6ead0aed75d7fa06b45d9f581632ffa9e680..f92c4993f65ae5477d69e11cb2a301cf9c7ab240
@@@ -74,7 -73,7 +74,8 @@@ MACHINE_START(SPEAR310, "ST-SPEAR310-EV
        .atag_offset    =       0x100,
        .map_io         =       spear3xx_map_io,
        .init_irq       =       spear3xx_init_irq,
 +      .handle_irq     =       vic_handle_irq,
        .timer          =       &spear3xx_timer,
        .init_machine   =       spear310_evb_init,
+       .restart        =       spear_restart,
  MACHINE_END
index e9751f970933078d462f3382330b5516c642c6b5,4239a70686c5a049841e04165fde71b3520477f8..105334ab70213e85a4f3c8f8909e5cb634879921
@@@ -72,7 -71,7 +72,8 @@@ MACHINE_START(SPEAR320, "ST-SPEAR320-EV
        .atag_offset    =       0x100,
        .map_io         =       spear3xx_map_io,
        .init_irq       =       spear3xx_init_irq,
 +      .handle_irq     =       vic_handle_irq,
        .timer          =       &spear3xx_timer,
        .init_machine   =       spear320_evb_init,
+       .restart        =       spear_restart,
  MACHINE_END
index ff139ed0a61ede2037bd6fcd5f78821aa5c93311,0a16559ba26421510f871509c58dd2f30f1707d7..c6e4254741cc71348696369e494ab79c86494060
@@@ -47,7 -46,7 +47,8 @@@ MACHINE_START(SPEAR600, "ST-SPEAR600-EV
        .atag_offset    =       0x100,
        .map_io         =       spear6xx_map_io,
        .init_irq       =       spear6xx_init_irq,
 +      .handle_irq     =       vic_handle_irq,
        .timer          =       &spear6xx_timer,
        .init_machine   =       spear600_evb_init,
+       .restart        =       spear_restart,
  MACHINE_END
index f6f03ce340fcafd4a0f72dff707ad3764a6321e2,aaaa17c9d21a7bd6e87ee40a4164b67d0d78a38b..e417a8383dbbcb4feae0dfdd2f59d956d8faeaa3
@@@ -131,8 -130,8 +131,9 @@@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegr
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_dt_init,
+       .restart        = tegra_assert_system_reset,
        .dt_compat      = tegra_dt_board_compat,
  MACHINE_END
index fd190a8dc6654c7e8fb200d85d596ffd15c26f2b,7eaa52de756cbfe128b44ebfcd8fa0c8d15d40a7..70ee674131f9fee9d77a189c12fafbb0dbd3af65
@@@ -188,7 -187,7 +188,8 @@@ MACHINE_START(HARMONY, "harmony"
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_harmony_init,
+       .restart        = tegra_assert_system_reset,
  MACHINE_END
index 0b7e1cfee70dacb03f9810a5f3ca90a316238737,28c97e3174073f6db4644342b11c5304c7dbbc51..33d6205ad307c07cafb34296444458c742e66419
@@@ -191,7 -190,7 +191,8 @@@ MACHINE_START(PAZ00, "Toshiba AC100 / D
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_paz00_init,
+       .restart        = tegra_assert_system_reset,
  MACHINE_END
index 7328379b1356b0fd8ac54d5f268bae71d7fdf11e,9b2eca1f5283c0c5c285a1942952ee971a6b8cd5..c1599eb8e0cb0acb791551f9b90a0d1f124da1e1
@@@ -285,9 -284,9 +285,10 @@@ MACHINE_START(SEABOARD, "seaboard"
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_seaboard_init,
+       .restart        = tegra_assert_system_reset,
  MACHINE_END
  
  MACHINE_START(KAEN, "kaen")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_kaen_init,
+       .restart        = tegra_assert_system_reset,
  MACHINE_END
  
  MACHINE_START(WARIO, "wario")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_wario_init,
+       .restart        = tegra_assert_system_reset,
  MACHINE_END
index 60a36a2e0be19696c9a53e96b1afaf716c93fee5,1fa9e48e8ec627ecad7889676e2901b9686a91ad..c242314a1db5e55e2a6552da18ef99497f100a7f
@@@ -177,7 -176,7 +177,8 @@@ MACHINE_START(TRIMSLICE, "trimslice"
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_init_irq,
 +      .handle_irq     = gic_handle_irq,
        .timer          = &tegra_timer,
        .init_machine   = tegra_trimslice_init,
+       .restart        = tegra_assert_system_reset,
  MACHINE_END
index 5f0f7060f3a1d4e658a7f7d883e40e92fe59546a,a75c9b83974880926ae84b1fc9920c89b5ec70d9..f30c69d91d994d8c432d5993fa6bafa45d7e91f4
@@@ -47,10 -46,10 +47,11 @@@ static void __init u300_init_machine(vo
  
  MACHINE_START(U300, MACH_U300_STRING)
        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
 -      .atag_offset    = BOOT_PARAMS_OFFSET,
 +      .atag_offset    = 0x100,
        .map_io         = u300_map_io,
        .init_irq       = u300_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &u300_timer,
        .init_machine   = u300_init_machine,
+       .restart        = u300_restart,
  MACHINE_END
Simple merge
index c83a1f379f7aba55d15adcf19e3caf2610760425,f1277ac92fac515f81377df735b81862cbc48b4a..63b8dd2b9f4d297132605432af9c17363870d517
@@@ -40,7 -39,7 +40,8 @@@ MACHINE_START(VERSATILE_AB, "ARM-Versat
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &versatile_timer,
        .init_machine   = versatile_init,
+       .restart        = versatile_restart,
  MACHINE_END
index 4d31eeb6c10136023c272bd10d9a562517e190ba,839bea633821c399260a0775777b5db345902efd..7aab79b665e71ee8bc57899817e29c76db046ac7
@@@ -108,7 -107,7 +108,8 @@@ MACHINE_START(VERSATILE_PB, "ARM-Versat
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
 +      .handle_irq     = vic_handle_irq,
        .timer          = &versatile_timer,
        .init_machine   = versatile_pb_init,
+       .restart        = versatile_restart,
  MACHINE_END
index 7aa07a8ce2323ff65606070a09cce2a338edd747,b9a465bd2d0ffb32af5c5f5e852489df20e4489c..6dd10e320ef68de0e16726cca8062bbc911cb6da
@@@ -449,6 -447,6 +448,7 @@@ MACHINE_START(VEXPRESS, "ARM-Versatile 
        .init_early     = v2m_init_early,
        .init_irq       = v2m_init_irq,
        .timer          = &v2m_timer,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = v2m_init,
+       .restart        = v2m_restart,
  MACHINE_END
Simple merge
diff --cc mm/vmalloc.c
Simple merge