hpd_low_cec_off = <1>;
/* bit4: enable feature, bit3~0: port number */
disable_port = <0x0>;
+ /* 1: enable, 0: disable */
+ scdc_force_en = <0>;
/* MAP_ADDR_MODULE_CBUS */
/* MAP_ADDR_MODULE_HIU */
/* MAP_ADDR_MODULE_HDMIRX_CAPB3 */
hpd_low_cec_off = <1>;
/* bit4: enable feature, bit3~0: port number */
disable_port = <0x0>;
+ /* 1: enable, 0: disable */
+ scdc_force_en = <0>;
/* MAP_ADDR_MODULE_CBUS */
/* MAP_ADDR_MODULE_HIU */
/* MAP_ADDR_MODULE_HDMIRX_CAPB3 */
hpd_low_cec_off = <1>;
/* bit4: enable feature, bit3~0: port number */
disable_port = <0x0>;
+ /* 1: enable, 0: disable */
+ scdc_force_en = <0>;
/* MAP_ADDR_MODULE_CBUS */
/* MAP_ADDR_MODULE_HIU */
/* MAP_ADDR_MODULE_HDMIRX_CAPB3 */
hpd_low_cec_off = <1>;
/* bit4: enable feature, bit3~0: port number */
disable_port = <0x0>;
+ /* 1: enable, 0: disable */
+ scdc_force_en = <0>;
/* MAP_ADDR_MODULE_CBUS */
/* MAP_ADDR_MODULE_HIU */
/* MAP_ADDR_MODULE_HDMIRX_CAPB3 */
rx.arc_port = 0x1;
rx_pr("not find arc_port, portB by default\n");
}
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "scdc_force_en",
+ &scdc_force_en);
+ if (ret) {
+ /* enable scdc accroding to edid version */
+ scdc_force_en = 0;
+ rx_pr("not find scdc_force_en, disable by default\n");
+ }
+
ret = of_reserved_mem_device_init(&(pdev->dev));
if (ret != 0)
rx_pr("warning: no rev cmd mem\n");
*
*
*/
-#define RX_VER2 "ver.2019/08/22"
+#define RX_VER2 "ver.2019/09/05"
/*print type*/
#define LOG_EN 0x01
/* cdr lock threshold */
int cdr_lock_level;
int clock_lock_th = 2;
+int scdc_force_en;
+
/*------------------------variable define end------------------------------*/
static int check_regmap_flag(unsigned int addr)
void hdmirx_20_init(void)
{
unsigned long data32;
- unsigned long scdc_en = rx.edid_ver;
+ unsigned long scdc_en =
+ scdc_force_en ? 1 : rx.edid_ver;
data32 = 0;
data32 |= 1 << 12; /* [12] vid_data_checken */
extern int top_intr_maskn_value;
extern int hbr_force_8ch;
extern int clock_lock_th;
+extern int scdc_force_en;
extern void rx_get_best_eq_setting(void);
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
extern void wr_reg_hhi_bits(unsigned int offset, unsigned int mask,
return pr_var(en_take_dtd_space, index);
if (set_pr_var(tmpbuf, earc_cap_ds_update_hpd_en, value, &index, ret))
return pr_var(earc_cap_ds_update_hpd_en, index);
+ if (set_pr_var(tmpbuf, scdc_force_en, value, &index, ret))
+ return pr_var(scdc_force_en, index);
return 0;
}
pr_var(clock_lock_th, i++);
pr_var(en_take_dtd_space, i++);
pr_var(earc_cap_ds_update_hpd_en, i++);
+ pr_var(scdc_force_en, i++);
}
void skip_frame(unsigned int cnt)