gpu: ipu-v3: Add ipu_dump()
authorSteve Longerbeam <slongerbeam@gmail.com>
Thu, 26 Jun 2014 01:05:55 +0000 (18:05 -0700)
committerPhilipp Zabel <p.zabel@pengutronix.de>
Tue, 2 Sep 2014 12:55:56 +0000 (14:55 +0200)
Adds ipu_dump() which dumps IPU register state to debug.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
drivers/gpu/ipu-v3/ipu-common.c
include/video/imx-ipu-v3.h

index 5c3d5269056eaeca7c57700f4d63f247c108cbf5..df65d2bca5221f6bd8cc6b29bf23bbe0fc3542a1 100644 (file)
@@ -1145,6 +1145,44 @@ static void ipu_irq_exit(struct ipu_soc *ipu)
        irq_domain_remove(ipu->domain);
 }
 
+void ipu_dump(struct ipu_soc *ipu)
+{
+       int i;
+
+       dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
+               ipu_cm_read(ipu, IPU_CONF));
+       dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
+               ipu_idmac_read(ipu, IDMAC_CONF));
+       dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
+               ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
+       dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
+               ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
+       dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
+               ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
+       dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
+               ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
+       dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
+               ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
+       dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
+               ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
+       dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
+               ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
+       dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
+               ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
+       dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
+               ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
+       dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
+               ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
+       dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
+               ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
+       dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
+               ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
+       for (i = 0; i < 15; i++)
+               dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
+                       ipu_cm_read(ipu, IPU_INT_CTRL(i)));
+}
+EXPORT_SYMBOL_GPL(ipu_dump);
+
 static int ipu_probe(struct platform_device *pdev)
 {
        const struct of_device_id *of_id =
index b41c17d5afc30c62f633c7ceaf73608b85785692..c74bf4a0520e5860d4548713794d0985d4eb0150 100644 (file)
@@ -151,6 +151,7 @@ int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
  */
 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
+void ipu_dump(struct ipu_soc *ipu);
 
 /*
  * IPU Image DMA Controller (idmac) functions