(s5p_mfc_version(dev) == 0xA01))
#define IS_MFCV11X(dev) (s5p_mfc_version(dev) == 0x1100)
#define IS_MFCV12X(dev) (s5p_mfc_version(dev) == 0x1200)
-#define FROM_MFCV11X(dev) (IS_MFCV11X(dev) || IS_MFCV12X(dev))
-#define FROM_MFCV10X(dev) (IS_MFCV10X(dev) || IS_MFCV11X(dev) || \
- IS_MFCV12X(dev))
+#define IS_MFCV13X(dev) (s5p_mfc_version(dev) == 0x1300)
+#define FROM_MFCV11X(dev) (IS_MFCV11X(dev) || IS_MFCV12X(dev) || \
+ IS_MFCV13X(dev))
+#define FROM_MFCV10X(dev) (IS_MFCV10X(dev) || FROM_MFCV11X(dev))
/* supported feature macros by F/W version */
#define FW_HAS_CONCEAL_CONTROL(dev) (FROM_MFCV10X(dev))
case IP_VER_MFC_9L_0:
version = 0x1200;
break;
+ case IP_VER_MFC_9R_0:
+ version = 0x1202;
+ break;
+ case IP_VER_MFC_9M_0:
+ version = 0x1021;
+ break;
+ case IP_VER_MFC_9M_1:
+ version = 0x1300;
+ break;
}
return version;
#define __REGS_MFC_V10_H __FILE__
/* SYSMMU Register */
-#define MFC_MMU0_BASE_ADDR 0x17880000
-#define MFC_MMU1_BASE_ADDR 0x178A0000
+#define MFC_MMU0_BASE_ADDR 0x18890000
+#define MFC_MMU1_BASE_ADDR 0x188B0000
#define MFC_MMU_SIZE 0x9000
#define MFC_MMU_INTERRUPT_STATUS 0x0060
#define MFC_MMU_FAULT_TRANS_INFO_RW_MASK 0x100000
#define MFC_MMU_FAULT_TRANS_INFO_AXID_MASK 0xFFFF
-#define HWFC_BASE_ADDR 0x17628000
+#define HWFC_BASE_ADDR 0x18A28000
#define HWFC_SIZE 0x100
#define HWFC_ENCODING_IDX 0x4