omap4: Add smc API to read AuxCoreBoot0 register
authorSantosh Shilimkar <santosh.shilimkar@ti.com>
Mon, 2 Aug 2010 10:18:18 +0000 (13:18 +0300)
committerTony Lindgren <tony@atomide.com>
Mon, 2 Aug 2010 10:18:18 +0000 (13:18 +0300)
This patch adds a secure API to read AuxCoreBoot0 register to
check the cpu boot status. It also moves the other smc APIs
to common omap44xx-smc.S. This APIs should not be marked as
__INIT because we need these to be present for CPU hotplug

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/omap-headsmp.S
arch/arm/mach-omap2/omap44xx-smc.S
arch/arm/plat-omap/include/plat/smp.h

index ef0e7a00dd6c6187732524cb1ecdcb1e6f74789e..6ae937a06cc1883f83af604845bf51c859f2adeb 100644 (file)
@@ -47,19 +47,3 @@ hold:        ldr     r12,=0x103
        b       secondary_startup
 END(omap_secondary_startup)
 
-
-ENTRY(omap_modify_auxcoreboot0)
-       stmfd   sp!, {r1-r12, lr}
-       ldr     r12, =0x104
-       dsb
-       smc     #0
-       ldmfd   sp!, {r1-r12, pc}
-END(omap_modify_auxcoreboot0)
-
-ENTRY(omap_auxcoreboot_addr)
-       stmfd   sp!, {r2-r12, lr}
-       ldr     r12, =0x105
-       dsb
-       smc     #0
-       ldmfd   sp!, {r2-r12, pc}
-END(omap_auxcoreboot_addr)
index f61c7771ca47e580cfebc4c654f49433290cfe02..1980dc31a1a2e85a28e0fc612eee5b41004db5d8 100644 (file)
@@ -30,3 +30,28 @@ ENTRY(omap_smc1)
        smc     #0
        ldmfd   sp!, {r2-r12, pc}
 END(omap_smc1)
+
+ENTRY(omap_modify_auxcoreboot0)
+       stmfd   sp!, {r1-r12, lr}
+       ldr     r12, =0x104
+       dsb
+       smc     #0
+       ldmfd   sp!, {r1-r12, pc}
+END(omap_modify_auxcoreboot0)
+
+ENTRY(omap_auxcoreboot_addr)
+       stmfd   sp!, {r2-r12, lr}
+       ldr     r12, =0x105
+       dsb
+       smc     #0
+       ldmfd   sp!, {r2-r12, pc}
+END(omap_auxcoreboot_addr)
+
+ENTRY(omap_read_auxcoreboot0)
+       stmfd   sp!, {r2-r12, lr}
+       ldr     r12, =0x103
+       dsb
+       smc     #0
+       mov     r0, r0, lsr #9
+       ldmfd   sp!, {r2-r12, pc}
+END(omap_read_auxcoreboot0)
index 8983d54c4fd2e95a8a30c2a5920376cb07893eb6..6a3ff65c030350e121649f5bed7cb9d9f8d76724 100644 (file)
@@ -30,6 +30,7 @@
 extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
 
 /*
  * We use Soft IRQ1 as the IPI