ASoC: fsl-sai: add default register map for regmap cache

FSL_SAI_TDR register is writable and not readable. According to
regmap_volatile() function, if FSL_SAI_TDR want to be volatile,
it should be readable. So we should remove FSL_SAI_TDR from volatile
register list.

If the flat cache don't have default register map, when do regcache_sync
operation, the non volatile and writable registers will be synchronised
to 0. FSL_SAI_TDR reigster will be written a 0 and cause channel swap.
So add default register map for flat cache, and such register will not
be written.

Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index a4435f5e3be910447f9168b4708d19140f3c1f4f..987fc5478abdfc7421e5e8baf33ff0458bdfa94e 100644 (file)
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -608,6 +608,22 @@ static const struct snd_soc_component_driver fsl_component = {
        .name           = "fsl-sai",
 };
 
+static struct reg_default fsl_sai_reg_defaults[] = {
+       {FSL_SAI_TCR1, 0},
+       {FSL_SAI_TCR2, 0},
+       {FSL_SAI_TCR3, 0},
+       {FSL_SAI_TCR4, 0},
+       {FSL_SAI_TCR5, 0},
+       {FSL_SAI_TDR,  0},
+       {FSL_SAI_TMR,  0},
+       {FSL_SAI_RCR1, 0},
+       {FSL_SAI_RCR2, 0},
+       {FSL_SAI_RCR3, 0},
+       {FSL_SAI_RCR4, 0},
+       {FSL_SAI_RCR5, 0},
+       {FSL_SAI_RMR,  0},
+};
+
 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
 {
        switch (reg) {
@@ -641,13 +657,11 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
        case FSL_SAI_RCSR:
        case FSL_SAI_TFR:
        case FSL_SAI_RFR:
-       case FSL_SAI_TDR:
        case FSL_SAI_RDR:
                return true;
        default:
                return false;
        }
-
 }
 
 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
@@ -680,6 +694,8 @@ static const struct regmap_config fsl_sai_regmap_config = {
        .val_bits = 32,
 
        .max_register = FSL_SAI_RMR,
+       .reg_defaults = fsl_sai_reg_defaults,
+       .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
        .readable_reg = fsl_sai_readable_reg,
        .volatile_reg = fsl_sai_volatile_reg,
        .writeable_reg = fsl_sai_writeable_reg,