uint16_t my_event_bits[4]; /* bit translations for IntSrc -->RDMISC2 */
};
-static const struct s626_enc_info s626_enc_chan_info[];
-
/* Counter overflow/index event flag masks for RDMISC2. */
#define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
#define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
debi_write(dev, k->my_crb, crb);
}
+static const struct s626_enc_info s626_enc_chan_info[] = {
+ {
+ .get_enable = get_enable_a,
+ .get_int_src = get_int_src_a,
+ .get_load_trig = get_load_trig_a,
+ .get_mode = get_mode_a,
+ .pulse_index = pulse_index_a,
+ .set_enable = set_enable_a,
+ .set_int_src = set_int_src_a,
+ .set_load_trig = set_load_trig_a,
+ .set_mode = set_mode_a,
+ .reset_cap_flags = reset_cap_flags_a,
+ .my_cra = LP_CR0A,
+ .my_crb = LP_CR0B,
+ .my_latch_lsw = LP_CNTR0ALSW,
+ .my_event_bits = EVBITS(0),
+ }, {
+ .get_enable = get_enable_a,
+ .get_int_src = get_int_src_a,
+ .get_load_trig = get_load_trig_a,
+ .get_mode = get_mode_a,
+ .pulse_index = pulse_index_a,
+ .set_enable = set_enable_a,
+ .set_int_src = set_int_src_a,
+ .set_load_trig = set_load_trig_a,
+ .set_mode = set_mode_a,
+ .reset_cap_flags = reset_cap_flags_a,
+ .my_cra = LP_CR1A,
+ .my_crb = LP_CR1B,
+ .my_latch_lsw = LP_CNTR1ALSW,
+ .my_event_bits = EVBITS(1),
+ }, {
+ .get_enable = get_enable_a,
+ .get_int_src = get_int_src_a,
+ .get_load_trig = get_load_trig_a,
+ .get_mode = get_mode_a,
+ .pulse_index = pulse_index_a,
+ .set_enable = set_enable_a,
+ .set_int_src = set_int_src_a,
+ .set_load_trig = set_load_trig_a,
+ .set_mode = set_mode_a,
+ .reset_cap_flags = reset_cap_flags_a,
+ .my_cra = LP_CR2A,
+ .my_crb = LP_CR2B,
+ .my_latch_lsw = LP_CNTR2ALSW,
+ .my_event_bits = EVBITS(2),
+ }, {
+ .get_enable = get_enable_b,
+ .get_int_src = get_int_src_b,
+ .get_load_trig = get_load_trig_b,
+ .get_mode = get_mode_b,
+ .pulse_index = pulse_index_b,
+ .set_enable = set_enable_b,
+ .set_int_src = set_int_src_b,
+ .set_load_trig = set_load_trig_b,
+ .set_mode = set_mode_b,
+ .reset_cap_flags = reset_cap_flags_b,
+ .my_cra = LP_CR0A,
+ .my_crb = LP_CR0B,
+ .my_latch_lsw = LP_CNTR0BLSW,
+ .my_event_bits = EVBITS(3),
+ }, {
+ .get_enable = get_enable_b,
+ .get_int_src = get_int_src_b,
+ .get_load_trig = get_load_trig_b,
+ .get_mode = get_mode_b,
+ .pulse_index = pulse_index_b,
+ .set_enable = set_enable_b,
+ .set_int_src = set_int_src_b,
+ .set_load_trig = set_load_trig_b,
+ .set_mode = set_mode_b,
+ .reset_cap_flags = reset_cap_flags_b,
+ .my_cra = LP_CR1A,
+ .my_crb = LP_CR1B,
+ .my_latch_lsw = LP_CNTR1BLSW,
+ .my_event_bits = EVBITS(4),
+ }, {
+ .get_enable = get_enable_b,
+ .get_int_src = get_int_src_b,
+ .get_load_trig = get_load_trig_b,
+ .get_mode = get_mode_b,
+ .pulse_index = pulse_index_b,
+ .set_enable = set_enable_b,
+ .set_int_src = set_int_src_b,
+ .set_load_trig = set_load_trig_b,
+ .set_mode = set_mode_b,
+ .reset_cap_flags = reset_cap_flags_b,
+ .my_cra = LP_CR2A,
+ .my_crb = LP_CR2B,
+ .my_latch_lsw = LP_CNTR2BLSW,
+ .my_event_bits = EVBITS(5),
+ },
+};
+
static unsigned int s626_ai_reg_to_uint(int data)
{
unsigned int tempdata;
}
}
-static const struct s626_enc_info s626_enc_chan_info[] = {
- {
- .get_enable = get_enable_a,
- .get_int_src = get_int_src_a,
- .get_load_trig = get_load_trig_a,
- .get_mode = get_mode_a,
- .pulse_index = pulse_index_a,
- .set_enable = set_enable_a,
- .set_int_src = set_int_src_a,
- .set_load_trig = set_load_trig_a,
- .set_mode = set_mode_a,
- .reset_cap_flags = reset_cap_flags_a,
- .my_cra = LP_CR0A,
- .my_crb = LP_CR0B,
- .my_latch_lsw = LP_CNTR0ALSW,
- .my_event_bits = EVBITS(0),
- }, {
- .get_enable = get_enable_a,
- .get_int_src = get_int_src_a,
- .get_load_trig = get_load_trig_a,
- .get_mode = get_mode_a,
- .pulse_index = pulse_index_a,
- .set_enable = set_enable_a,
- .set_int_src = set_int_src_a,
- .set_load_trig = set_load_trig_a,
- .set_mode = set_mode_a,
- .reset_cap_flags = reset_cap_flags_a,
- .my_cra = LP_CR1A,
- .my_crb = LP_CR1B,
- .my_latch_lsw = LP_CNTR1ALSW,
- .my_event_bits = EVBITS(1),
- }, {
- .get_enable = get_enable_a,
- .get_int_src = get_int_src_a,
- .get_load_trig = get_load_trig_a,
- .get_mode = get_mode_a,
- .pulse_index = pulse_index_a,
- .set_enable = set_enable_a,
- .set_int_src = set_int_src_a,
- .set_load_trig = set_load_trig_a,
- .set_mode = set_mode_a,
- .reset_cap_flags = reset_cap_flags_a,
- .my_cra = LP_CR2A,
- .my_crb = LP_CR2B,
- .my_latch_lsw = LP_CNTR2ALSW,
- .my_event_bits = EVBITS(2),
- }, {
- .get_enable = get_enable_b,
- .get_int_src = get_int_src_b,
- .get_load_trig = get_load_trig_b,
- .get_mode = get_mode_b,
- .pulse_index = pulse_index_b,
- .set_enable = set_enable_b,
- .set_int_src = set_int_src_b,
- .set_load_trig = set_load_trig_b,
- .set_mode = set_mode_b,
- .reset_cap_flags = reset_cap_flags_b,
- .my_cra = LP_CR0A,
- .my_crb = LP_CR0B,
- .my_latch_lsw = LP_CNTR0BLSW,
- .my_event_bits = EVBITS(3),
- }, {
- .get_enable = get_enable_b,
- .get_int_src = get_int_src_b,
- .get_load_trig = get_load_trig_b,
- .get_mode = get_mode_b,
- .pulse_index = pulse_index_b,
- .set_enable = set_enable_b,
- .set_int_src = set_int_src_b,
- .set_load_trig = set_load_trig_b,
- .set_mode = set_mode_b,
- .reset_cap_flags = reset_cap_flags_b,
- .my_cra = LP_CR1A,
- .my_crb = LP_CR1B,
- .my_latch_lsw = LP_CNTR1BLSW,
- .my_event_bits = EVBITS(4),
- }, {
- .get_enable = get_enable_b,
- .get_int_src = get_int_src_b,
- .get_load_trig = get_load_trig_b,
- .get_mode = get_mode_b,
- .pulse_index = pulse_index_b,
- .set_enable = set_enable_b,
- .set_int_src = set_int_src_b,
- .set_load_trig = set_load_trig_b,
- .set_mode = set_mode_b,
- .reset_cap_flags = reset_cap_flags_b,
- .my_cra = LP_CR2A,
- .my_crb = LP_CR2B,
- .my_latch_lsw = LP_CNTR2BLSW,
- .my_event_bits = EVBITS(5),
- },
-};
-
static void counters_init(struct comedi_device *dev)
{
int chan;