drm/i915: explicitly set up PIPECONF (and gamma table) on haswell

Again we don't really support different settings, so don't let the
BIOS sneak stuff through.

Since the motivation for this patch series is to ensure we have the
correct gamma table mode selected also add the required write to the
GAMMA_MODE register to select the 8bit legacy table.

And since I find lowercase letters in #defines offensive, also
bikeshed those.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4058eaa198947e03b077fc76eba2d6a9489eef2f..2102ff32ee200fe61acd01f36a6ee6eeedd61bcd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3672,9 +3672,9 @@
 #define _GAMMA_MODE_B          0x4ac80
 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
 #define GAMMA_MODE_MODE_MASK   (3 << 0)
-#define GAMMA_MODE_MODE_8bit   (0 << 0)
-#define GAMMA_MODE_MODE_10bit  (1 << 0)
-#define GAMMA_MODE_MODE_12bit  (2 << 0)
+#define GAMMA_MODE_MODE_8BIT   (0 << 0)
+#define GAMMA_MODE_MODE_10BIT  (1 << 0)
+#define GAMMA_MODE_MODE_12BIT  (2 << 0)
 #define GAMMA_MODE_MODE_SPLIT  (3 << 0)
 
 /* interrupts */

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a6b4bee9034ccfdd01276a292057d2863fdf41d6..06b1180c4c1685b60c48445aad89f8d410d0a9de 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5437,13 +5437,11 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
        enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
        uint32_t val;
 
-       val = I915_READ(PIPECONF(cpu_transcoder));
+       val = 0;
 
-       val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
        if (intel_crtc->config.dither)
                val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-       val &= ~PIPECONF_INTERLACE_MASK_HSW;
        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
                val |= PIPECONF_INTERLACED_ILK;
        else
@@ -5451,6 +5449,9 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
 
        I915_WRITE(PIPECONF(cpu_transcoder), val);
        POSTING_READ(PIPECONF(cpu_transcoder));
+
+       I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
+       POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
 }
 
 static bool ironlake_compute_clocks(struct drm_crtc *crtc,