[RAMEN9610-7789] [9610] fbdev: dpu20: enabled decon enhance path

rebased

Change-Id: Ia071733b6d4651b96eef3cce6dde5cc7bfa2d90d
Signed-off-by: ChiHun Won <chihun.won@samsung.com>

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
index 6559d20dabfa01d692cbbb766be60d6645990ec6..ea7e41949aa45d5996fcb3c7662092b3206c2bc6 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
@@ -86,6 +86,11 @@ enum decon_scaler_path {
        SCALERPATH_VG0  = 0x1,
 };
 
+enum decon_enhance_path {
+       ENHANCEPATH_ENHANCE_ALL_OFF     = 0x0,
+       ENHANCEPATH_DQE_ON              = 0x2,
+};
+
 enum decon_path_cfg {
        PATH_CON_ID_DSIM_IF0 = 0,
        PATH_CON_ID_DSIM_IF1 = 1,
@@ -295,6 +300,11 @@ void __decon_dump(u32 id, void __iomem *regs, void __iomem *base_regs, bool dsc_
 void decon_reg_set_int(u32 id, struct decon_mode_info *psr, u32 en);
 int decon_reg_get_interrupt_and_clear(u32 id, u32 *ext_irq);
 
+void decon_reg_set_data_path(u32 id, enum decon_data_path d_path,
+               enum decon_scaler_path s_path, enum decon_enhance_path e_path);
+void decon_reg_get_data_path(u32 id, enum decon_data_path *d_path,
+               enum decon_scaler_path *s_path, enum decon_enhance_path *e_path);
+
 void decon_reg_set_start_crc(u32 id, u32 en);
 void decon_reg_set_select_crc_bits(u32 id, u32 bit_sel);
 void decon_reg_get_crc_data(u32 id, u32 *w0_data, u32 *w1_data);
@@ -307,6 +317,7 @@ int decon_check_global_limitation(struct decon_device *decon,
 
 /* TODO: this will be removed later */
 void decon_reg_update_req_global(u32 id);
+void decon_reg_update_req_dqe(u32 id);
 /*********************************************************************/
 
 #endif /* __SAMSUNG_DECON_CAL_H__ */

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
index 18c61997ccb37e3e3b1ca1486923261633e05e4d..5c0ec9d1b661b1a07f13de51fd862728e31d64ba 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
@@ -281,16 +281,29 @@ static void decon_reg_set_blender_bg_image_size(u32 id,
 
 }
 
-static void decon_reg_set_data_path(u32 id, enum decon_data_path d_path,
-               enum decon_scaler_path s_path)
+void decon_reg_set_data_path(u32 id, enum decon_data_path d_path,
+               enum decon_scaler_path s_path, enum decon_enhance_path e_path)
 {
        u32 val, mask;
 
-       val = SCALER_PATH_F(s_path) | COMP_OUTIF_PATH_F(d_path);
-       mask = SCALER_PATH_MASK | COMP_OUTIF_PATH_MASK;
+       val = SCALER_PATH_F(s_path)
+               | ENHANCE_PATH_F(e_path)
+               | COMP_OUTIF_PATH_F(d_path);
+       mask = SCALER_PATH_MASK | ENHANCE_PATH_MASK | COMP_OUTIF_PATH_MASK;
        decon_write_mask(id, DATA_PATH_CONTROL_2, val, mask);
 }
 
+void decon_reg_get_data_path(u32 id, enum decon_data_path *d_path,
+               enum decon_scaler_path *s_path, enum decon_enhance_path *e_path)
+{
+       u32 val;
+
+       val = decon_read(id, DATA_PATH_CONTROL_2);
+       *d_path = COMP_OUTIF_PATH_GET(val);
+       *s_path = SCALER_PATH_GET(val);
+       *e_path = ENHANCE_PATH_GET(val);
+}
+
 /*
  * Check major configuration of data_path_control
  *    DSCC[7]
@@ -1373,6 +1386,7 @@ static void decon_reg_configure_lcd(u32 id, struct decon_param *p)
        u32 overlap_w = 0;
        enum decon_data_path d_path = DPATH_DSCENC0_OUTFIFO0_DSIMIF0;
        enum decon_scaler_path s_path = SCALERPATH_OFF;
+       enum decon_enhance_path e_path = ENHANCEPATH_ENHANCE_ALL_OFF;
 
        struct decon_lcd *lcd_info = p->lcd_info;
        struct decon_mode_info *psr = &p->psr;
@@ -1397,7 +1411,7 @@ static void decon_reg_configure_lcd(u32 id, struct decon_param *p)
                        decon_err("[decon%d] dsc_cnt=%d : not supported\n",
                                id, lcd_info->dsc_cnt);
 
-               decon_reg_set_data_path(id, d_path, s_path);
+               decon_reg_set_data_path(id, d_path, s_path, e_path);
                /* call decon_reg_config_data_path_size () inside */
                dsc_reg_init(id, p, overlap_w, 0);
        } else {
@@ -1408,7 +1422,7 @@ static void decon_reg_configure_lcd(u32 id, struct decon_param *p)
                                DPATH_NOCOMP_OUTFIFO0_DSIMIF0 :
                                DECON2_NOCOMP_OUTFIFO0_DPIF;
 
-               decon_reg_set_data_path(id, d_path, s_path);
+               decon_reg_set_data_path(id, d_path, s_path, e_path);
 
                decon_reg_config_data_path_size(id,
                        lcd_info->xres, lcd_info->yres, overlap_w, NULL, p);
@@ -1426,6 +1440,7 @@ static void decon_reg_init_probe(u32 id, u32 dsi_idx, struct decon_param *p)
        struct decon_mode_info *psr = &p->psr;
        enum decon_data_path d_path = DPATH_DSCENC0_OUTFIFO0_DSIMIF0;
        enum decon_scaler_path s_path = SCALERPATH_OFF;
+       enum decon_enhance_path e_path = ENHANCEPATH_ENHANCE_ALL_OFF;
        enum decon_rgb_order rgb_order = DECON_RGB;
        enum decon_dsi_mode dsi_mode = psr->dsi_mode;
        u32 overlap_w = 0; /* default=0 : range=[0, 32] & (multiples of 2) */
@@ -1464,7 +1479,7 @@ static void decon_reg_init_probe(u32 id, u32 dsi_idx, struct decon_param *p)
                        decon_err("[decon%d] dsc_cnt=%d : not supported\n",
                                id, lcd_info->dsc_cnt);
 
-               decon_reg_set_data_path(id, d_path, s_path);
+               decon_reg_set_data_path(id, d_path, s_path, e_path);
                /* call decon_reg_config_data_path_size () inside */
                dsc_reg_init(id, p, overlap_w, 0);
        } else {
@@ -1475,7 +1490,7 @@ static void decon_reg_init_probe(u32 id, u32 dsi_idx, struct decon_param *p)
                                DPATH_NOCOMP_OUTFIFO0_DSIMIF0 :
                                DECON2_NOCOMP_OUTFIFO0_DPIF;
 
-               decon_reg_set_data_path(id, d_path, s_path);
+               decon_reg_set_data_path(id, d_path, s_path, e_path);
 
                decon_reg_config_data_path_size(id,
                        lcd_info->xres, lcd_info->yres, overlap_w, NULL, p);
@@ -1513,7 +1528,9 @@ static int decon_reg_stop_perframe(u32 id, u32 dsi_idx,
 
        /* perframe stop */
        decon_reg_per_frame_off(id);
-
+#if defined(CONFIG_EXYNOS_DECON_DQE)
+       decon_reg_update_req_dqe(id);
+#endif
        decon_reg_update_req_global(id);
 
        /* timeout : 1 / fps + 20% margin */
@@ -1539,7 +1556,9 @@ static int decon_reg_stop_inst(u32 id, u32 dsi_idx, struct decon_mode_info *psr,
 
        /* instant stop */
        decon_reg_direct_on_off(id, 0);
-
+#if defined(CONFIG_EXYNOS_DECON_DQE)
+       decon_reg_update_req_dqe(id);
+#endif
        decon_reg_update_req_global(id);
 
 #if defined(CONFIG_EXYNOS_DISPLAYPORT)
@@ -1725,11 +1744,21 @@ void decon_reg_update_req_global(u32 id)
                        SHADOW_REG_UPDATE_REQ_GLOBAL);
 }
 
+void decon_reg_update_req_dqe(u32 id)
+{
+       if (id != 0)
+               return;
+
+       decon_write_mask(id, SHADOW_REG_UPDATE_REQ, ~0,
+                       SHADOW_REG_UPDATE_REQ_DQE);
+}
+
 int decon_reg_init(u32 id, u32 dsi_idx, struct decon_param *p)
 {
        struct decon_lcd *lcd_info = p->lcd_info;
        struct decon_mode_info *psr = &p->psr;
        enum decon_scaler_path s_path = SCALERPATH_OFF;
+       enum decon_enhance_path e_path = ENHANCEPATH_ENHANCE_ALL_OFF;
 
        /*
         * DECON does not need to start, if DECON is already
@@ -1771,7 +1800,7 @@ int decon_reg_init(u32 id, u32 dsi_idx, struct decon_param *p)
 
        /* FIXME: DECON_T dedicated to PRE_WB */
        if (p->psr.out_type == DECON_OUT_WB)
-               decon_reg_set_data_path(id, DPATH_WBPRE_ONLY, s_path);
+               decon_reg_set_data_path(id, DPATH_WBPRE_ONLY, s_path, e_path);
 
        /* asserted interrupt should be cleared before initializing decon hw */
        decon_reg_clear_int_all(id);
@@ -1787,6 +1816,9 @@ int decon_reg_start(u32 id, struct decon_mode_info *psr)
        int ret = 0;
 
        decon_reg_direct_on_off(id, 1);
+#if defined(CONFIG_EXYNOS_DECON_DQE)
+       decon_reg_update_req_dqe(id);
+#endif
        decon_reg_update_req_global(id);
 
        /*

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h
index 503928ef504935281ed523dde21ba6dce0555dcf..249f7b7953c675518f07c9676ce48c1cec10d548 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h
@@ -139,6 +139,7 @@
 
 #define SHADOW_REG_UPDATE_REQ                  0x0060
 #define SHADOW_REG_UPDATE_REQ_GLOBAL           (1 << 31)
+#define SHADOW_REG_UPDATE_REQ_DQE              (1 << 28)
 #define SHADOW_REG_UPDATE_REQ_WIN(_win)                (1 << (_win))
 #define SHADOW_REG_UPDATE_REQ_FOR_DECON                (0x3f)
 
@@ -315,9 +316,9 @@
 #define SCALER_PATH_F(_v)                      ((_v) << 24)
 #define SCALER_PATH_MASK                       (0x3 << 24)
 #define SCALER_PATH_GET(_v)                    (((_v) >> 24) & 0x3)
-#define EHNANCE_PATH_F(_v)                     ((_v) << 12)
-#define EHNANCE_PATH_MASK                      (0x7 << 12)
-#define EHNANCE_PATH_GET(_v)                   (((_v) >> 12) & 0x7)
+#define ENHANCE_PATH_F(_v)                     ((_v) << 12)
+#define ENHANCE_PATH_MASK                      (0x7 << 12)
+#define ENHANCE_PATH_GET(_v)                   (((_v) >> 12) & 0x7)
 #define COMP_OUTIF_PATH_F(_v)                  ((_v) << 0)
 #define COMP_OUTIF_PATH_MASK                   (0xff << 0)
 #define COMP_OUTIF_PATH_GET(_v)                        (((_v) >> 0) & 0xff)