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ARCv2: [axs103_smp] Reduce clk for SMP FPGA configs
authorVineet Gupta <Vineet.Gupta1@synopsys.com>
Fri, 11 Sep 2015 23:32:22 +0000 (16:32 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 12 Sep 2015 02:34:01 +0000 (19:34 -0700)
Newer bitfiles needs the reduced clk even for SMP builds

Cc: <stable@vger.kernel.org> #4.2
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arch/arc/plat-axs10x/axs10x.c patch | blob | blame | history

diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index ad9825d4026aefe0b51d0f85037a2858f1ccda83..0a77b19e1df8db1d37af0346e36a4b53254ca272 100644 (file)
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -402,6 +402,8 @@ static void __init axs103_early_init(void)
        unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
        if (num_cores > 2)
                arc_set_core_freq(50 * 1000000);
+       else if (num_cores == 2)
+               arc_set_core_freq(75 * 1000000);
 #endif
 
        switch (arc_get_core_freq()/1000000) {