drivers: net: xgene: XFI PCS reset when link is down

This patch fixes the link recovery issue, by doing PCS reset
when the link is down.

Signed-off-by: Fushen Chen <fchen@apm.com>
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
index 179a44dceb299d07940589f1dcbc47acd5870a83..8a8d055008948ed022cda4065aba8345035290cf 100644 (file)
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
@@ -124,6 +124,12 @@ enum xgene_enet_rm {
 #define MAC_READ_REG_OFFSET            0x0c
 #define MAC_COMMAND_DONE_REG_OFFSET    0x10
 
+#define PCS_ADDR_REG_OFFSET            0x00
+#define PCS_COMMAND_REG_OFFSET         0x04
+#define PCS_WRITE_REG_OFFSET           0x08
+#define PCS_READ_REG_OFFSET            0x0c
+#define PCS_COMMAND_DONE_REG_OFFSET    0x10
+
 #define MII_MGMT_CONFIG_ADDR           0x20
 #define MII_MGMT_COMMAND_ADDR          0x24
 #define MII_MGMT_ADDRESS_ADDR          0x28

diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
index a727da8260c1e97d8f6287e60d671dbf14840fa2..01a9aaf496694225fabd29b805119005b83a0f66 100644 (file)
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
@@ -1433,6 +1433,7 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
        } else {
                pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
                pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
+               pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET;
        }
        pdata->rx_buff_cnt = NUM_PKT_BUF;
 

diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
index 217546e5714aea490c4250ea7b61cc6ea18e268e..53f4a165a56fc6885f918071bceb645c22da14f6 100644 (file)
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
@@ -196,6 +196,7 @@ struct xgene_enet_pdata {
        void __iomem *mcx_mac_addr;
        void __iomem *mcx_mac_csr_addr;
        void __iomem *base_addr;
+       void __iomem *pcs_addr;
        void __iomem *ring_csr_addr;
        void __iomem *ring_cmd_addr;
        int phy_mode;

diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
index d53c05336c442de6d1e5d1b8148c718b10f27139..4087dba6ea84ad9453629278c3ddcf2a8c6ea8e5 100644 (file)
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
@@ -84,6 +84,21 @@ static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,
                           wr_addr);
 }
 
+static void xgene_enet_wr_pcs(struct xgene_enet_pdata *pdata,
+                             u32 wr_addr, u32 wr_data)
+{
+       void __iomem *addr, *wr, *cmd, *cmd_done;
+
+       addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
+       wr = pdata->pcs_addr + PCS_WRITE_REG_OFFSET;
+       cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
+       cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;
+
+       if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
+               netdev_err(pdata->ndev, "PCS write failed, addr: %04x\n",
+                          wr_addr);
+}
+
 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
                              u32 offset, u32 *val)
 {
@@ -122,6 +137,7 @@ static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
 
        return true;
 }
+
 static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
                              u32 rd_addr, u32 *rd_data)
 {
@@ -137,6 +153,21 @@ static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
                           rd_addr);
 }
 
+static void xgene_enet_rd_pcs(struct xgene_enet_pdata *pdata,
+                             u32 rd_addr, u32 *rd_data)
+{
+       void __iomem *addr, *rd, *cmd, *cmd_done;
+
+       addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
+       rd = pdata->pcs_addr + PCS_READ_REG_OFFSET;
+       cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
+       cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;
+
+       if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
+               netdev_err(pdata->ndev, "PCS read failed, addr: %04x\n",
+                          rd_addr);
+}
+
 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
 {
        struct net_device *ndev = pdata->ndev;
@@ -171,6 +202,15 @@ static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
        xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
 }
 
+static void xgene_pcs_reset(struct xgene_enet_pdata *pdata)
+{
+       u32 data;
+
+       xgene_enet_rd_pcs(pdata, PCS_CONTROL_1, &data);
+       xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data | PCS_CTRL_PCS_RST);
+       xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data & ~PCS_CTRL_PCS_RST);
+}
+
 static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
 {
        u32 addr0, addr1;
@@ -379,6 +419,8 @@ static void xgene_enet_link_state(struct work_struct *work)
                        netdev_info(ndev, "Link is Down\n");
                }
                poll_interval = PHY_POLL_LINK_OFF;
+
+               xgene_pcs_reset(pdata);
        }
 
        schedule_delayed_work(&pdata->link_work, poll_interval);

diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h
index f1ea485f916bc70e9105825a8511cdaee2e5236d..360ccbd9556654430c34bde6250d4759a9aed81b 100644 (file)
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h
@@ -24,6 +24,7 @@
 #define X2_BLOCK_ETH_MAC_CSR_OFFSET    0x3000
 #define BLOCK_AXG_MAC_OFFSET           0x0800
 #define BLOCK_AXG_MAC_CSR_OFFSET       0x2000
+#define BLOCK_PCS_OFFSET               0x3800
 
 #define XGENET_CONFIG_REG_ADDR         0x20
 #define XGENET_SRST_ADDR               0x00
@@ -72,6 +73,9 @@
 #define XG_MCX_ICM_CONFIG0_REG_0_ADDR  0x00e0
 #define XG_MCX_ICM_CONFIG2_REG_0_ADDR  0x00e8
 
+#define PCS_CONTROL_1                  0x0000
+#define PCS_CTRL_PCS_RST               BIT(15)
+
 extern const struct xgene_mac_ops xgene_xgmac_ops;
 extern const struct xgene_port_ops xgene_xgport_ops;