drm/i915: Use topdown allocation for PPGTT PDEs on gen6/7
authorBen Widawsky <benjamin.widawsky@intel.com>
Wed, 7 May 2014 05:21:30 +0000 (22:21 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 7 May 2014 08:01:41 +0000 (10:01 +0200)
It was always the intention to do the topdown allocation for context
objects (Chris' idea originally). Unfortunately, I never managed to land
the patch, but someone else did, so now we can use it.

As a reminder, hardware contexts never need to be in the precious GTT
aperture space - which is what is what happens with the normal bottom up
allocation we do today. Doing a top down allocation increases the odds
that the HW contexts can get out of the way, especially with per FD
contexts as is done in full PPGTT

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_gtt.c

index 1827b4b349a1a6a8f70d44b743b1c75867aba51e..84dcb4e00d4c4754b59d1bdff403277ea861a253 100644 (file)
@@ -1035,8 +1035,7 @@ alloc:
                                                  &ppgtt->node, GEN6_PD_SIZE,
                                                  GEN6_PD_ALIGN, 0,
                                                  0, dev_priv->gtt.base.total,
-                                                 DRM_MM_SEARCH_DEFAULT,
-                                                 DRM_MM_CREATE_DEFAULT);
+                                                 DRM_MM_TOPDOWN);
        if (ret == -ENOSPC && !retried) {
                ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
                                               GEN6_PD_SIZE, GEN6_PD_ALIGN,