x86/speculation: Rework speculative_store_bypass_update()

commit 0270be3e34efb05a88bc4c422572ece038ef3608 upstream

The upcoming support for the virtual SPEC_CTRL MSR on AMD needs to reuse
speculative_store_bypass_update() to avoid code duplication. Add an
argument for supplying a thread info (TIF) value and create a wrapper
speculative_store_bypass_update_current() which is used at the existing
call site.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h
index 6e2874049afdc8cf3785845f778f7169eb8d064a..82b6c5a0d61e057d271e9131536494709402d0d5 100644 (file)
--- a/arch/x86/include/asm/spec-ctrl.h
+++ b/arch/x86/include/asm/spec-ctrl.h
@@ -42,6 +42,11 @@ extern void speculative_store_bypass_ht_init(void);
 static inline void speculative_store_bypass_ht_init(void) { }
 #endif
 
-extern void speculative_store_bypass_update(void);
+extern void speculative_store_bypass_update(unsigned long tif);
+
+static inline void speculative_store_bypass_update_current(void)
+{
+       speculative_store_bypass_update(current_thread_info()->flags);
+}
 
 #endif

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 82422a04b5066c1b77ca052c700928466f499a59..f2f0c1b3bf50a3ccaa55f5b0c8588bc3dab9c155 100644 (file)
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -598,7 +598,7 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
         * mitigation until it is next scheduled.
         */
        if (task == current && update)
-               speculative_store_bypass_update();
+               speculative_store_bypass_update_current();
 
        return 0;
 }

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 70f129dcc66fb49ed5d644c8b79e6eb28326e51a..988a98f34c6646f37124314c834dcfb8671e783a 100644 (file)
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -415,10 +415,10 @@ static __always_inline void __speculative_store_bypass_update(unsigned long tifn
                intel_set_ssb_state(tifn);
 }
 
-void speculative_store_bypass_update(void)
+void speculative_store_bypass_update(unsigned long tif)
 {
        preempt_disable();
-       __speculative_store_bypass_update(current_thread_info()->flags);
+       __speculative_store_bypass_update(tif);
        preempt_enable();
 }