drm/i915/chv: Remove pre-production workarounds

-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
-WaDisableDopClockGating:chv

v2: Remove pre-production WA instead of restricting them
based on revision id (Ville)

For: VIZ-4090
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 300d7e503f96d374204dd91e871d7d3107d56b37..5764936e3a223754ab62b47694c8626fefb8976d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6958,18 +6958,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
        /* WaDisableSDEUnitClockGating:chv */
        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-       /* WaDisableGunitClockGating:chv (pre-production hw) */
-       I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
-                  GINT_DIS);
-
-       /* WaDisableFfDopClockGating:chv (pre-production hw) */
-       I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
-                  _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
-
-       /* WaDisableDopClockGating:chv (pre-production hw) */
-       I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
-                  GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f457146ff6a46cca11169bb1358fd99c822fb403..70fcf2aa0ca25cf8e8e67adfeaaa44c3b97b140f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -795,14 +795,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
                  STALL_DOP_GATING_DISABLE);
 
-       /* WaDisableDopClockGating:chv (pre-production hw) */
-       WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
-                 DOP_CLOCK_GATING_DISABLE);
-
-       /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
-       WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
-                 GEN8_SAMPLER_POWER_BYPASS_DIS);
-
        return 0;
 }