clk: tegra: change post IDDQ release delay to 5us

Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1c36b8a72bd27d8c7cdc3e15f43991606a69a390..695ccb436cec907c4f39e738f1c46187f89072a5 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw)
                val = pll_readl(pll->params->iddq_reg, pll);
                val &= ~BIT(pll->params->iddq_bit_idx);
                pll_writel(val, pll->params->iddq_reg, pll);
-               udelay(2);
+               udelay(5);
        }
 
        if (pll->params->reset_reg) {