m68knommu: move inclusion of ColdFire v4 cache registers
authorGreg Ungerer <gerg@uclinux.org>
Tue, 9 Nov 2010 00:40:44 +0000 (10:40 +1000)
committerGreg Ungerer <gerg@uclinux.org>
Wed, 5 Jan 2011 05:19:18 +0000 (15:19 +1000)
Move the inclusion of the version 4 cache controller registers so that
it is with all the other register bit flag definitions. This makes it
consistent with the other version core inclusion points, and means we
don't need "#ifdef"ery in odd-ball places for these definitions.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
arch/m68k/include/asm/cacheflush_no.h
arch/m68k/include/asm/m5407sim.h
arch/m68k/include/asm/m54xxsim.h
arch/m68k/include/asm/mcfcache.h

index e295923020d3c2854bfe5ad65221227557712056..52b11ac9a30c3217a96a6092b7199cfa0a26c565 100644 (file)
@@ -5,9 +5,7 @@
  * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
  */
 #include <linux/mm.h>
-#if defined(CONFIG_M5407) || defined(CONFIG_M54xx)
-#include <asm/m54xxacr.h>
-#endif
+#include <asm/mcfsim.h>
 
 #define flush_cache_all()                      __flush_cache_all()
 #define flush_cache_mm(mm)                     do { } while (0)
index ddfff88629fee6e9ae14c5bff37a55292015632a..75f5c28a551d996c0dd128cef99fcb56fe2095c0 100644 (file)
@@ -17,6 +17,8 @@
 #define        CPU_NAME                "COLDFIRE(m5407)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m54xxacr.h>
+
 /*
  *     Define the 5407 SIM register set addresses.
  */
index a08a7ae776b16721dca056edd966b4823b2d9b59..462ae5328441ab163df7497bd4061c9573608735 100644 (file)
@@ -8,6 +8,8 @@
 #define        CPU_NAME                "COLDFIRE(m54xx)"
 #define        CPU_INSTR_PER_JIFFY     2
 
+#include <asm/m54xxacr.h>
+
 #define MCFINT_VECBASE         64
 
 /*
index 437686b62feaf38f76fe892f714720e59bd66826..2b3a6cfaaac0159c84a8b30a337308408991ab8e 100644 (file)
 
 #if defined(CONFIG_M5407) || defined(CONFIG_M54xx)
 
-#include <asm/m54xxacr.h>
-
 .macro CACHE_ENABLE
        /* invalidate whole cache */
        movel   #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0