dt-bindings: qoriq-clock: Add coreclk

ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk".  If present, this clock will be used for the core PLLs.

Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 6ed469c66b32f42c4bfb62849ce5451618d5067e..6498e1fdbb33a2a4661638d501dca842b500bb0d 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -57,6 +57,11 @@ Optional properties:
 - clocks: If clock-frequency is not specified, sysclk may be provided
        as an input clock.  Either clock-frequency or clocks must be
        provided.
+       A second input clock, called "coreclk", may be provided if
+       core PLLs are based on a different input clock from the
+       platform PLL.
+- clock-names: Required if a coreclk is present.  Valid names are
+       "sysclk" and "coreclk".
 
 2. Clock Provider
 
@@ -73,6 +78,7 @@ second cell is the clock index for the specified type.
        2       hwaccel         index (n in CLKCGnHWACSR)
        3       fman            0 for fm1, 1 for fm2
        4       platform pll    0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+       5       coreclk         must be 0
 
 3. Example