clk: tegra: Fix cclk_lp divisor register

[ Upstream commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e ]

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index a2d163f759b4502df2ad4f1f4e5d738904da67a7..07f5203df01c05574a211a4b8672b2c0c107b17e 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -964,7 +964,7 @@ static void __init tegra30_super_clk_init(void)
         * U71 divider of cclk_lp.
         */
        clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
-                               clk_base + SUPER_CCLKG_DIVIDER, 0,
+                               clk_base + SUPER_CCLKLP_DIVIDER, 0,
                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
        clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);