ARM: dts: Enable support for USB 3.0 PHY controller for exynos5420
authorVivek Gautam <gautam.vivek@samsung.com>
Thu, 15 May 2014 21:37:03 +0000 (06:37 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Mon, 19 May 2014 14:13:53 +0000 (23:13 +0900)
Add device tree nodes for USB 3.0 PHY present alongwith
USB 3.0 controller Exynos 5420 SoC. This phy driver is
based on generic phy framework.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/boot/dts/exynos5420.dtsi

index 384f7a2f91ed01e3fcfd2412e2e9d00b5b8766fa..31d99b0a20226308da12b214c7162884d9ed73ef 100644 (file)
@@ -47,6 +47,8 @@
                spi0 = &spi_0;
                spi1 = &spi_1;
                spi2 = &spi_2;
+               usbdrdphy0 = &usbdrd_phy0;
+               usbdrdphy1 = &usbdrd_phy1;
        };
 
        cpus {
                clock-names = "secss";
                samsung,power-domain = <&g2d_pd>;
        };
+
+       usbdrd_phy0: phy@12100000 {
+               compatible = "samsung,exynos5420-usbdrd-phy";
+               reg = <0x12100000 0x100>;
+               clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+               clock-names = "phy", "ref";
+               samsung,pmu-syscon = <&pmu_system_controller>;
+               #phy-cells = <1>;
+       };
+
+       usbdrd_phy1: phy@12500000 {
+               compatible = "samsung,exynos5420-usbdrd-phy";
+               reg = <0x12500000 0x100>;
+               clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+               clock-names = "phy", "ref";
+               samsung,pmu-syscon = <&pmu_system_controller>;
+               #phy-cells = <1>;
+       };
 };