irqchip/gic-v3-its: Add VPENDBASER/VPROPBASER accessors

V{PEND,PROP}BASER being 64bit registers, they need some ad-hoc
accessors on 32bit, specially given that VPENDBASER contains
a Valid bit, making the access a bit convoluted.

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 27475904e0966f1caafffb23b199d4d4c2bb920e..8d45e88feac905bf6348f03f437a1ed219f51d83 100644 (file)
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -291,5 +291,33 @@ static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
  */
 #define gits_write_cwriter(v, c)       __gic_writeq_nonatomic(v, c)
 
+/*
+ * GITS_VPROPBASER - hi and lo bits may be accessed independently.
+ */
+#define gits_write_vpropbaser(v, c)    __gic_writeq_nonatomic(v, c)
+
+/*
+ * GITS_VPENDBASER - the Valid bit must be cleared before changing
+ * anything else.
+ */
+static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
+{
+       u32 tmp;
+
+       tmp = readl_relaxed(addr + 4);
+       if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
+               tmp &= ~(GICR_VPENDBASER_Valid >> 32);
+               writel_relaxed(tmp, addr + 4);
+       }
+
+       /*
+        * Use the fact that __gic_writeq_nonatomic writes the second
+        * half of the 64bit quantity after the first.
+        */
+       __gic_writeq_nonatomic(val, addr);
+}
+
+#define gits_read_vpendbaser(c)                __gic_readq_nonatomic(c)
+
 #endif /* !__ASSEMBLY__ */
 #endif /* !__ASM_ARCH_GICV3_H */

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 8cef47fa2218d4941c06cb7d80bdd6375b5f36fd..0d2a53457c3080462ed02ca15b3f2ad18cfe4b8b 100644 (file)
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -133,5 +133,10 @@ static inline void gic_write_bpr1(u32 val)
 #define gicr_write_pendbaser(v, c)     writeq_relaxed(v, c)
 #define gicr_read_pendbaser(c)         readq_relaxed(c)
 
+#define gits_write_vpropbaser(v, c)    writeq_relaxed(v, c)
+
+#define gits_write_vpendbaser(v, c)    writeq_relaxed(v, c)
+#define gits_read_vpendbaser(c)                readq_relaxed(c)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_GICV3_H */

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 7c6fd8f3e36c916cb73b5451febd81eda8a7ce95..17ba0d732f125cbe72444a4ca9a88f1924559c5d 100644 (file)
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -212,6 +212,11 @@
 #define LPI_PROP_GROUP1                        (1 << 1)
 #define LPI_PROP_ENABLED               (1 << 0)
 
+#define GICR_VPENDBASER_Dirty          (1ULL << 60)
+#define GICR_VPENDBASER_PendingLast    (1ULL << 61)
+#define GICR_VPENDBASER_IDAI           (1ULL << 62)
+#define GICR_VPENDBASER_Valid          (1ULL << 63)
+
 /*
  * ITS registers, offsets from ITS_base
  */