aclk_khz = v4l2_subdev_call(decon->out_sd[0], core, ioctl,
EXYNOS_DPU_GET_ACLK, NULL) / 1000U;
decon_info("%s:DPU_ACLK(%ld khz)\n", __func__, aclk_khz);
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
decon_info("MIF(%lu), INT(%lu), DISP(%lu), total bw(%u, %u)\n",
cal_dfs_get_rate(ACPM_DVFS_MIF),
cal_dfs_get_rate(ACPM_DVFS_INT),
aclk_khz = v4l2_subdev_call(decon->out_sd[0], core, ioctl,
EXYNOS_DPU_GET_ACLK, NULL) / 1000U;
decon_info("%s:DPU_ACLK(%ld khz)\n", __func__, aclk_khz);
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
decon_info("MIF(%lu), INT(%lu), DISP(%lu), total bw(%u, %u)\n",
cal_dfs_get_rate(ACPM_DVFS_MIF),
cal_dfs_get_rate(ACPM_DVFS_INT),
pm_stay_awake(decon->dev);
dev_warn(decon->dev, "pm_stay_awake");
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
decon->bts.ops->bts_acquire_bw(decon);
#endif
decon->cur_using_dpp = 0;
decon_dpp_stop(decon, false);
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
decon->bts.ops->bts_release_bw(decon);
#endif
decon_dpp_stop(decon, false);
}
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
decon->bts.ops->bts_release_bw(decon);
#endif
decon_update_hdr_info(decon, regs);
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
/* add calc and update bw : cur > prev */
decon->bts.ops->bts_calc_bw(decon, regs);
decon->bts.ops->bts_update_bw(decon, regs, 0);
decon_update_vgf_info(decon, regs, false);
#endif
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
/* add update bw : cur < prev */
decon->bts.ops->bts_update_bw(decon, regs, 1);
#endif
decon_init_low_persistence_mode(decon);
dpu_init_cursor_mode(decon);
-#if defined(CONFIG_EXYNOS9610_BTS)
+#if defined(CONFIG_EXYNOS_BTS)
decon->bts.ops = &decon_bts_control;
decon->bts.ops->bts_init(decon);
#endif