int i, ret = 0;
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
const char *clk_div_parents[1];
- u32 clk_reg, cfg;
+ u32 clk_reg;
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
clk_reg = 0;
if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
return PTR_ERR(host->cfg_div_clk);
- /* Ensure clock starts in "auto" mode, not "always on" */
- cfg = readl(host->regs + SD_EMMC_CFG);
- cfg &= ~CFG_CLK_ALWAYS_ON;
- cfg |= CFG_AUTO_CLK;
- writel(cfg, host->regs + SD_EMMC_CFG);
-
ret = clk_prepare_enable(host->cfg_div_clk);
if (ret)
return ret;
if (ret)
goto err_core_clk;
+ /* set config to sane default */
+ meson_mmc_cfg_init(host);
+
/* Stop execution */
writel(0, host->regs + SD_EMMC_START);
writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);
- /* set config to sane default */
- meson_mmc_cfg_init(host);
-
ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
meson_mmc_irq_thread, IRQF_SHARED,
NULL, host);