clk: mediatek: add the option for determining PLL source clock

[ Upstream commit c955bf3998efa3355790a4d8c82874582f1bc727 ]

Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f5d6b70ce189372602f2c6f8aaa1d2694ba8e65e..210ce8e8025eee5e53ada86377cded41b5f8e8b4 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -216,6 +216,7 @@ struct mtk_pll_data {
        uint32_t pcw_reg;
        int pcw_shift;
        const struct mtk_pll_div_table *div_table;
+       const char *parent_name;
 };
 
 void mtk_clk_register_plls(struct device_node *node,

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index a409142e93462dd0eb7fc599f43479a26b2c695c..7598477ff60f156447aec210e753a30d396c5788 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -303,7 +303,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
        init.name = data->name;
        init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
        init.ops = &mtk_pll_ops;
-       init.parent_names = &parent_name;
+       if (data->parent_name)
+               init.parent_names = &data->parent_name;
+       else
+               init.parent_names = &parent_name;
        init.num_parents = 1;
 
        clk = clk_register(NULL, &pll->hw);