ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default

It seams at least on twl5031 that the ARXR2_APGA_CTL register
does not have the same default value as it is written in
the TRM.
Since the codec part of the PM chip has not been actually
changed according to TI, assuming, that all version has
the same problem, so writing there the TRM value.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 30b7bbaf6aed5bf6c67f3cf1458110893dff31b3..c667ca5a8a9e16225321b0d7ee3cc4df16345715 100644 (file)
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -289,6 +289,9 @@ static void twl4030_init_chip(struct platform_device *pdev)
                TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
                TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
 
+       /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
+       twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
+
        /* Machine dependent setup */
        if (!setup)
                return;