ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs

On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE
and 18 steps for big core (200-1700 MHz). Add respective cooling cells.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 9b46b9fbac4e774b1542cde204f949bcc791b730..bf3c6f1ec4ee3c48b9a01a2b31ce97a87d67a00b 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -32,6 +32,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu1: cpu@101 {
@@ -41,6 +44,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu2: cpu@102 {
@@ -50,6 +56,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu3: cpu@103 {
@@ -59,6 +68,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu4: cpu@0 {
@@ -69,6 +81,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu5: cpu@1 {
@@ -78,6 +93,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu6: cpu@2 {
@@ -87,6 +105,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu7: cpu@3 {
@@ -96,6 +117,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
        };
 };