ARM: 7716/1: bcm281xx: Add L2 support for Rev A2 chips

Rev A2 SoCs have an unorthodox memory re-mapping and this needs
to be reflected in the cache operations.
This patch adds new outer cache functions for the l2x0 driver
to support this SoC revision. It also adds a new compatible
value for the cache to enable this functionality.

Updates from V1:
- remove section 1 altogether and note that in comments
- simplify section selection caused by section 1 removal
- BUG_ON just in case section 1 shows up

Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index cbef09b5c8a71672924360e028176488f03f2faa..69ddf9fad2dcccc36bbaa330b96170d2eb9b213d 100644 (file)
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -16,6 +16,9 @@ Required properties:
      performs the same operation).
        "marvell,"aurora-outer-cache: Marvell Controller designed to be
         compatible with the ARM one with outer cache mode.
+       "bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+       offset needs to be added to the address before passing down to the L2
+       cache controller
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped

diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c33f095e44cf695dbfaa5d325e094c7630..5e48c85abc2f5027333d498d767ef7548afeb67e 100644 (file)
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -47,10 +47,10 @@
        };
 
        L2: l2-cache {
-                   compatible = "arm,pl310-cache";
-                   reg = <0x3ff20000 0x1000>;
-                   cache-unified;
-                   cache-level = <2>;
+               compatible = "bcm,bcm11351-a2-pl310-cache";
+               reg = <0x3ff20000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
        };
 
        timer@35006000 {

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c465faca51b06b05ed50c27962b8b169198ea909..d70e0aba0c9d9b4a0d10a78c627e159b1bf90d9b 100644 (file)
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
        }
 }
 
+/*
+ * For certain Broadcom SoCs, depending on the address range, different offsets
+ * need to be added to the address before passing it to L2 for
+ * invalidation/clean/flush
+ *
+ * Section Address Range              Offset        EMI
+ *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
+ *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
+ *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
+ *
+ * When the start and end addresses have crossed two different sections, we
+ * need to break the L2 operation into two, each within its own section.
+ * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
+ * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
+ * 0xC0000000 - 0xC0001000
+ *
+ * Note 1:
+ * By breaking a single L2 operation into two, we may potentially suffer some
+ * performance hit, but keep in mind the cross section case is very rare
+ *
+ * Note 2:
+ * We do not need to handle the case when the start address is in
+ * Section 1 and the end address is in Section 3, since it is not a valid use
+ * case
+ *
+ * Note 3:
+ * Section 1 in practical terms can no longer be used on rev A2. Because of
+ * that the code does not need to handle section 1 at all.
+ *
+ */
+#define BCM_SYS_EMI_START_ADDR        0x40000000UL
+#define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
+
+#define BCM_SYS_EMI_OFFSET            0x40000000UL
+#define BCM_VC_EMI_OFFSET             0x80000000UL
+
+static inline int bcm_addr_is_sys_emi(unsigned long addr)
+{
+       return (addr >= BCM_SYS_EMI_START_ADDR) &&
+               (addr < BCM_VC_EMI_SEC3_START_ADDR);
+}
+
+static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
+{
+       if (bcm_addr_is_sys_emi(addr))
+               return addr + BCM_SYS_EMI_OFFSET;
+       else
+               return addr + BCM_VC_EMI_OFFSET;
+}
+
+static void bcm_inv_range(unsigned long start, unsigned long end)
+{
+       unsigned long new_start, new_end;
+
+       BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+       if (unlikely(end <= start))
+               return;
+
+       new_start = bcm_l2_phys_addr(start);
+       new_end = bcm_l2_phys_addr(end);
+
+       /* normal case, no cross section between start and end */
+       if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+               l2x0_inv_range(new_start, new_end);
+               return;
+       }
+
+       /* They cross sections, so it can only be a cross from section
+        * 2 to section 3
+        */
+       l2x0_inv_range(new_start,
+               bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+       l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+               new_end);
+}
+
+static void bcm_clean_range(unsigned long start, unsigned long end)
+{
+       unsigned long new_start, new_end;
+
+       BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+       if (unlikely(end <= start))
+               return;
+
+       if ((end - start) >= l2x0_size) {
+               l2x0_clean_all();
+               return;
+       }
+
+       new_start = bcm_l2_phys_addr(start);
+       new_end = bcm_l2_phys_addr(end);
+
+       /* normal case, no cross section between start and end */
+       if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+               l2x0_clean_range(new_start, new_end);
+               return;
+       }
+
+       /* They cross sections, so it can only be a cross from section
+        * 2 to section 3
+        */
+       l2x0_clean_range(new_start,
+               bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+       l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+               new_end);
+}
+
+static void bcm_flush_range(unsigned long start, unsigned long end)
+{
+       unsigned long new_start, new_end;
+
+       BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+       if (unlikely(end <= start))
+               return;
+
+       if ((end - start) >= l2x0_size) {
+               l2x0_flush_all();
+               return;
+       }
+
+       new_start = bcm_l2_phys_addr(start);
+       new_end = bcm_l2_phys_addr(end);
+
+       /* normal case, no cross section between start and end */
+       if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+               l2x0_flush_range(new_start, new_end);
+               return;
+       }
+
+       /* They cross sections, so it can only be a cross from section
+        * 2 to section 3
+        */
+       l2x0_flush_range(new_start,
+               bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+       l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+               new_end);
+}
+
 static void __init l2x0_of_setup(const struct device_node *np,
                                 u32 *aux_val, u32 *aux_mask)
 {
@@ -765,6 +906,21 @@ static const struct l2x0_of_data aurora_no_outer_data = {
        },
 };
 
+static const struct l2x0_of_data bcm_l2x0_data = {
+       .setup = pl310_of_setup,
+       .save  = pl310_save,
+       .outer_cache = {
+               .resume      = pl310_resume,
+               .inv_range   = bcm_inv_range,
+               .clean_range = bcm_clean_range,
+               .flush_range = bcm_flush_range,
+               .sync        = l2x0_cache_sync,
+               .flush_all   = l2x0_flush_all,
+               .inv_all     = l2x0_inv_all,
+               .disable     = l2x0_disable,
+       },
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
        { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
        { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
@@ -773,6 +929,8 @@ static const struct of_device_id l2x0_ids[] __initconst = {
          .data = (void *)&aurora_no_outer_data},
        { .compatible = "marvell,aurora-outer-cache",
          .data = (void *)&aurora_with_outer_data},
+       { .compatible = "bcm,bcm11351-a2-pl310-cache",
+         .data = (void *)&bcm_l2x0_data},
        {}
 };