drm: extract dp link bw helpers

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 7ecaa11f35f6f29e66dff97da4e2a3629552f10b..3c4cccd0d753a91197deed7dee96ed87c3224b8f 100644 (file)
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -297,3 +297,31 @@ void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
                mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
 }
 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
+
+u8 drm_dp_link_rate_to_bw_code(int link_rate)
+{
+       switch (link_rate) {
+       case 162000:
+       default:
+               return DP_LINK_BW_1_62;
+       case 270000:
+               return DP_LINK_BW_2_7;
+       case 540000:
+               return DP_LINK_BW_5_4;
+       }
+}
+EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
+
+int drm_dp_bw_code_to_link_rate(u8 link_bw)
+{
+       switch (link_bw) {
+       case DP_LINK_BW_1_62:
+       default:
+               return 162000;
+       case DP_LINK_BW_2_7:
+               return 270000;
+       case DP_LINK_BW_5_4:
+               return 540000;
+       }
+}
+EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3cb180e38ca13bdc1cba6d0eec17dceda72c540d..f7b7bfc455e2b33143651e40da32128585e1a8df 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -108,10 +108,7 @@ intel_edp_link_config(struct intel_encoder *intel_encoder,
        struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 
        *lane_num = intel_dp->lane_count;
-       if (intel_dp->link_bw == DP_LINK_BW_1_62)
-               *link_bw = 162000;
-       else if (intel_dp->link_bw == DP_LINK_BW_2_7)
-               *link_bw = 270000;
+       *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 }
 
 int

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 5e23ab27ae466f298264471040c4d7885883a8b1..093e17d07574503bfc803b744d5125bfeca9350c 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -347,37 +347,11 @@ static int dp_get_max_dp_pix_clock(int link_rate,
        return (link_rate * lane_num * 8) / bpp;
 }
 
-static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
-{
-       switch (dpcd[DP_MAX_LINK_RATE]) {
-       case DP_LINK_BW_1_62:
-       default:
-               return 162000;
-       case DP_LINK_BW_2_7:
-               return 270000;
-       case DP_LINK_BW_5_4:
-               return 540000;
-       }
-}
-
 static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
 {
        return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
 }
 
-static u8 dp_get_dp_link_rate_coded(int link_rate)
-{
-       switch (link_rate) {
-       case 162000:
-       default:
-               return DP_LINK_BW_1_62;
-       case 270000:
-               return DP_LINK_BW_2_7;
-       case 540000:
-               return DP_LINK_BW_5_4;
-       }
-}
-
 /***** radeon specific DP functions *****/
 
 /* First get the min lane# when low rate is used according to pixel clock
@@ -389,7 +363,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
                                        int pix_clock)
 {
        int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
-       int max_link_rate = dp_get_max_link_rate(dpcd);
+       int max_link_rate = drm_dp_max_link_rate(dpcd);
        int max_lane_num = dp_get_max_lane_number(dpcd);
        int lane_num;
        int max_dp_pix_clock;
@@ -427,7 +401,7 @@ static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
                        return 540000;
        }
 
-       return dp_get_max_link_rate(dpcd);
+       return drm_dp_max_link_rate(dpcd);
 }
 
 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
@@ -692,7 +666,7 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
        radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 
        /* set the link rate on the sink */
-       tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
+       tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
        radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 
        /* start training on the source */

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 60bd8d3ae6ebe8a9b4668b044d67a72161fd3130..455f8e05ca3f80c73345358b26e3aaf059810496 100644 (file)
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -338,4 +338,12 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
 void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 
+u8 drm_dp_link_rate_to_bw_code(int link_rate);
+int drm_dp_bw_code_to_link_rate(u8 link_bw);
+
+static inline int
+drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+       return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
+}
 #endif /* _DRM_DP_HELPER_H_ */