drm/i915/bdw: Do not write the Semaphore Sync Registers in GEN8+

These do not exist anymore.

Spotted while reading through intel_ringbuffer.c

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 279488addf3f6bd7afb194bf29479a9228390460..0eaaaec78bae9a1748ba4566f01c70068799e2d6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1746,14 +1746,15 @@ int intel_ring_cacheline_align(struct intel_engine_cs *ring)
 
 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
 {
-       struct drm_i915_private *dev_priv = ring->dev->dev_private;
+       struct drm_device *dev = ring->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
 
        BUG_ON(ring->outstanding_lazy_seqno);
 
-       if (INTEL_INFO(ring->dev)->gen >= 6) {
+       if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
                I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
                I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
-               if (HAS_VEBOX(ring->dev))
+               if (HAS_VEBOX(dev))
                        I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
        }