AD1938_DAC_R4_VOL, 0, 0xFF, 1),
/* ADC switch control */
- SOC_DOUBLE("ADC1 Switch", AD1938_ADC_CTRL0, AD1938_ADCL1_MUTE, AD1938_ADCR1_MUTE, 1, 1),
- SOC_DOUBLE("ADC2 Switch", AD1938_ADC_CTRL0, AD1938_ADCL2_MUTE, AD1938_ADCR2_MUTE, 1, 1),
+ SOC_DOUBLE("ADC1 Switch", AD1938_ADC_CTRL0, AD1938_ADCL1_MUTE,
+ AD1938_ADCR1_MUTE, 1, 1),
+ SOC_DOUBLE("ADC2 Switch", AD1938_ADC_CTRL0, AD1938_ADCL2_MUTE,
+ AD1938_ADCR2_MUTE, 1, 1),
/* DAC switch control */
- SOC_DOUBLE("DAC1 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL1_MUTE, AD1938_DACR1_MUTE, 1, 1),
- SOC_DOUBLE("DAC2 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL2_MUTE, AD1938_DACR2_MUTE, 1, 1),
- SOC_DOUBLE("DAC3 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL3_MUTE, AD1938_DACR3_MUTE, 1, 1),
- SOC_DOUBLE("DAC4 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL4_MUTE, AD1938_DACR4_MUTE, 1, 1),
+ SOC_DOUBLE("DAC1 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL1_MUTE,
+ AD1938_DACR1_MUTE, 1, 1),
+ SOC_DOUBLE("DAC2 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL2_MUTE,
+ AD1938_DACR2_MUTE, 1, 1),
+ SOC_DOUBLE("DAC3 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL3_MUTE,
+ AD1938_DACR3_MUTE, 1, 1),
+ SOC_DOUBLE("DAC4 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL4_MUTE,
+ AD1938_DACR4_MUTE, 1, 1),
/* ADC high-pass filter */
SOC_SINGLE("ADC High Pass Filter Switch", AD1938_ADC_CTRL0,
int reg;
reg = codec->read(codec, AD1938_DAC_CTRL2);
- reg = (mute > 0) ? reg | AD1938_DAC_MASTER_MUTE : reg & (~AD1938_DAC_MASTER_MUTE);
+ reg = (mute > 0) ? reg | AD1938_DAC_MASTER_MUTE : reg &
+ (~AD1938_DAC_MASTER_MUTE);
codec->write(codec, AD1938_DAC_CTRL2, reg);
return 0;
static inline int ad1938_pll_powerctrl(struct snd_soc_codec *codec, int cmd)
{
int reg = codec->read(codec, AD1938_PLL_CLK_CTRL0);
- reg = (cmd > 0) ? reg & (~AD1938_PLL_POWERDOWN) : reg | AD1938_PLL_POWERDOWN;
+ reg = (cmd > 0) ? reg & (~AD1938_PLL_POWERDOWN) : reg |
+ AD1938_PLL_POWERDOWN;
codec->write(codec, AD1938_PLL_CLK_CTRL0, reg);
return 0;
adc_reg = codec->read(codec, AD1938_ADC_CTRL2);
dac_reg = codec->read(codec, AD1938_DAC_CTRL1);
- /* At present, the driver only support AUX ADC mode(SND_SOC_DAIFMT_I2S with TDM)
- * and ADC&DAC TDM mode(SND_SOC_DAIFMT_DSP_A)
+ /* At present, the driver only support AUX ADC mode(SND_SOC_DAIFMT_I2S
+ * with TDM) and ADC&DAC TDM mode(SND_SOC_DAIFMT_DSP_A)
*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
* read from the ad1938 register space
*/
-static unsigned int ad1938_read_reg(struct snd_soc_codec *codec, unsigned int reg)
+static unsigned int ad1938_read_reg(struct snd_soc_codec *codec,
+ unsigned int reg)
{
char w_buf[AD1938_SPI_BUFLEN];
char r_buf[AD1938_SPI_BUFLEN];
ad1938_codec = codec;
/* default setting for ad1938 */
- codec->write(codec, AD1938_DAC_CHNL_MUTE, 0x0); /* unmute dac channels */
- codec->write(codec, AD1938_DAC_CTRL2, 0x1A); /* de-emphasis: 48kHz, powedown dac */
- codec->write(codec, AD1938_DAC_CTRL0, 0x21); /* powerdown dac, dac tdm mode */
- codec->write(codec, AD1938_ADC_CTRL0, 0x3); /* high-pass filter enable */
- codec->write(codec, AD1938_ADC_CTRL1, 0x43); /* sata delay=1, adc aux mode */
- codec->write(codec, AD1938_PLL_CLK_CTRL0, 0x9D); /* pll input:mclki/xi */
+
+ /* unmute dac channels */
+ codec->write(codec, AD1938_DAC_CHNL_MUTE, 0x0);
+ /* de-emphasis: 48kHz, powedown dac */
+ codec->write(codec, AD1938_DAC_CTRL2, 0x1A);
+ /* powerdown dac, dac in tdm mode */
+ codec->write(codec, AD1938_DAC_CTRL0, 0x41);
+ /* high-pass filter enable */
+ codec->write(codec, AD1938_ADC_CTRL0, 0x3);
+ /* sata delay=1, adc aux mode */
+ codec->write(codec, AD1938_ADC_CTRL1, 0x43);
+ /* pll input: mclki/xi */
+ codec->write(codec, AD1938_PLL_CLK_CTRL0, 0x9D);
codec->write(codec, AD1938_PLL_CLK_CTRL1, 0x04);
ad1938_fill_cache(codec);