dt: Add bindings for IDT VersaClock 5P49V5925

IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
Input clock source can be taken only from external reference clock.

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 66ef0a009b953417b7a279c13018d28666c17f10..05a245c9df08fe48738a1d3e27e6bd45711b4a50 100644 (file)
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -8,6 +8,7 @@ generators providing from 3 to 12 output clocks.
 Required properties:
 - compatible:  shall be one of
                "idt,5p49v5923"
+               "idt,5p49v5925"
                "idt,5p49v5933"
                "idt,5p49v5935"
                "idt,5p49v6901"
@@ -15,6 +16,7 @@ Required properties:
 - #clock-cells:        from common clock binding; shall be set to 1.
 - clocks:      from common clock binding; list of parent clock handles,
                - 5p49v5923 and
+                 5p49v5925 and
                  5p49v6901: (required) either or both of XTAL or CLKIN
                                        reference clock.
                - 5p49v5933 and
@@ -23,6 +25,7 @@ Required properties:
                                        clock.
 - clock-names: from common clock binding; clock input names, can be
                - 5p49v5923 and
+                 5p49v5925 and
                  5p49v6901: (required) either or both of "xin", "clkin".
                - 5p49v5933 and
                - 5p49v5935: (optional) property not present or "clkin".
@@ -42,6 +45,7 @@ clock specifier, the following mapping applies:
        1 -- OUT1
        2 -- OUT4
 
+5P49V5925 and
 5P49V5935:
        0 -- OUT0_SEL_I2CB
        1 -- OUT1