drm/i915: set CDCLK if DPLL0 enabled during resuming from S3

Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then
driver needs to set CDCLK to avoid display corruption if DPLL0 enabled.

References: https://bugs.freedesktop.org/show_bug.cgi?id=91697
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Cooper Chiou <cooper.chiou@intel.com>
Reviewed-by: Wei Shun Chang <wei.shun.chang@intel.com>
Tested-by: Gary Wang <gary.c.wang@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Gavin Hindman <gavin.hindman@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Xiong Y Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Gary Wang <gary.c.wang@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 53f5476bc4bb88625dbbb824eadd78eb15761b31..8ea9821261abc868fd49ea70a3b8266735740860 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5712,16 +5712,13 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
        /* enable PG1 and Misc I/O */
        intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
 
-       /* DPLL0 already enabed !? */
-       if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
-               DRM_DEBUG_DRIVER("DPLL0 already running\n");
-               return;
+       /* DPLL0 not enabled (happens on early BIOS versions) */
+       if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
+               /* enable DPLL0 */
+               required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
+               skl_dpll0_enable(dev_priv, required_vco);
        }
 
-       /* enable DPLL0 */
-       required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-       skl_dpll0_enable(dev_priv, required_vco);
-
        /* set CDCLK to the frequency the BIOS chose */
        skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);