#include "../comedidev.h"
-#include "mite.h"
-
#define AO_VALUE_OFFSET 0x00
#define AO_CHAN_OFFSET 0x0c
#define AO_STATUS_OFFSET 0x10
};
struct ni_670x_private {
-
- struct mite_struct *mite;
+ void __iomem *mmio;
int boardtype;
int dio;
unsigned int ao_readback[32];
for (i = 0; i < insn->n; i++) {
/* First write in channel register which channel to use */
writel(((chan & 15) << 1) | ((chan & 16) >> 4),
- devpriv->mite->daq_io_addr + AO_CHAN_OFFSET);
+ devpriv->mmio + AO_CHAN_OFFSET);
/* write channel value */
- writel(data[i], devpriv->mite->daq_io_addr + AO_VALUE_OFFSET);
+ writel(data[i], devpriv->mmio + AO_VALUE_OFFSET);
devpriv->ao_readback[chan] = data[i];
}
unsigned int *data)
{
struct ni_670x_private *devpriv = dev->private;
- void __iomem *io_addr = devpriv->mite->daq_io_addr +
- DIO_PORT0_DATA_OFFSET;
+ void __iomem *io_addr = devpriv->mmio + DIO_PORT0_DATA_OFFSET;
if (comedi_dio_update_state(s, data))
writel(s->state, io_addr);
if (ret)
return ret;
- writel(s->io_bits, devpriv->mite->daq_io_addr + DIO_PORT0_DIR_OFFSET);
+ writel(s->io_bits, devpriv->mmio + DIO_PORT0_DIR_OFFSET);
return insn->n;
}
+/* ripped from mite.h and mite_setup2() to avoid mite dependancy */
+#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
+#define WENAB (1 << 7) /* window enable */
+
+static int ni_670x_mite_init(struct pci_dev *pcidev)
+{
+ void __iomem *mite_base;
+ u32 main_phys_addr;
+
+ /* ioremap the MITE registers (BAR 0) temporarily */
+ mite_base = pci_ioremap_bar(pcidev, 0);
+ if (!mite_base)
+ return -ENOMEM;
+
+ /* set data window to main registers (BAR 1) */
+ main_phys_addr = pci_resource_start(pcidev, 1);
+ writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
+
+ /* finished with MITE registers */
+ iounmap(mite_base);
+ return 0;
+}
+
static int ni_670x_auto_attach(struct comedi_device *dev,
unsigned long context)
{
if (!devpriv)
return -ENOMEM;
- devpriv->mite = mite_alloc(pcidev);
- if (!devpriv->mite)
- return -ENOMEM;
-
- ret = mite_setup(devpriv->mite);
- if (ret < 0) {
- dev_warn(dev->class_dev, "error setting up mite\n");
+ ret = ni_670x_mite_init(pcidev);
+ if (ret)
return ret;
- }
+
+ devpriv->mmio = pci_ioremap_bar(pcidev, 1);
+ if (!devpriv->mmio)
+ return -ENOMEM;
ret = comedi_alloc_subdevices(dev, 2);
if (ret)
s->insn_config = ni_670x_dio_insn_config;
/* Config of misc registers */
- writel(0x10, devpriv->mite->daq_io_addr + MISC_CONTROL_OFFSET);
+ writel(0x10, devpriv->mmio + MISC_CONTROL_OFFSET);
/* Config of ao registers */
- writel(0x00, devpriv->mite->daq_io_addr + AO_CONTROL_OFFSET);
+ writel(0x00, devpriv->mmio + AO_CONTROL_OFFSET);
return 0;
}
if (s)
kfree(s->range_table_list);
}
- if (devpriv)
- mite_detach(devpriv->mite);
+ if (devpriv && devpriv->mmio)
+ iounmap(devpriv->mmio);
comedi_pci_disable(dev);
}