drm/i915: don't change VDD AUX status in panel power functions
authorJesse Barnes <jbarnes@virtuousgeek.org>
Wed, 8 Sep 2010 19:42:03 +0000 (12:42 -0700)
committerChris Wilson <chris@chris-wilson.co.uk>
Wed, 8 Sep 2010 20:20:25 +0000 (21:20 +0100)
Mode set sequence outlines when the AUX VDD bit should be set and
cleared, and it's separate from the panel power sequence.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_dp.c

index effbbe0915ecf84186235de3125b359e0ca546c2..153a5934b2e1334757386e37c2abc107a771fbb5 100644 (file)
@@ -783,7 +783,7 @@ static bool ironlake_edp_panel_on (struct drm_device *dev)
                DRM_ERROR("panel on wait timed out: 0x%08x\n",
                          I915_READ(PCH_PP_STATUS));
 
-       pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
+       pp &= ~(PANEL_UNLOCK_REGS);
        pp |= PANEL_POWER_RESET; /* restore panel reset bit */
        I915_WRITE(PCH_PP_CONTROL, pp);
        POSTING_READ(PCH_PP_CONTROL);
@@ -811,7 +811,7 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
                          I915_READ(PCH_PP_STATUS));
 
        /* Make sure VDD is enabled so DP AUX will work */
-       pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */
+       pp |= PANEL_POWER_RESET; /* restore panel reset bit */
        I915_WRITE(PCH_PP_CONTROL, pp);
        POSTING_READ(PCH_PP_CONTROL);
 }