s5p_mfc_release_hwlock_dev(dev);
-#ifdef NAL_Q_ENABLE
- dev->nal_q_handle = s5p_mfc_nal_q_create(dev);
- if (dev->nal_q_handle == NULL)
- mfc_err_dev("NAL Q: Can't create nal q\n");
-#endif
+ if (dev->pdata->nal_q) {
+ dev->nal_q_handle = s5p_mfc_nal_q_create(dev);
+ if (dev->nal_q_handle == NULL)
+ mfc_err_dev("NAL Q: Can't create nal q\n");
+ }
return ret;
}
#endif
-#ifdef NAL_Q_ENABLE
if (dev->nal_q_handle) {
ret = s5p_mfc_nal_q_destroy(dev, dev->nal_q_handle);
if (ret) {
goto err_release;
}
}
-#endif
}
s5p_mfc_qos_off(ctx);
mutex_unlock(&dev->mfc_mutex);
return ret;
-#if defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) || defined(NAL_Q_ENABLE)
err_release:
s5p_mfc_release_hwlock_ctx(ctx);
mutex_unlock(&dev->mfc_mutex);
return ret;
-#endif
err_release_try:
s5p_mfc_release_hwlock_ctx(ctx);
of_property_read_u32(np, "ip_ver", &pdata->ip_ver);
of_property_read_u32(np, "debug_mode", &pdata->debug_mode);
+ of_property_read_u32(np, "nal_q", &pdata->nal_q);
#ifdef CONFIG_MFC_USE_BUS_DEVFREQ
of_property_read_u32(np, "num_qos_steps", &pdata->num_qos_steps);
of_property_read_u32(np, "max_qos_steps", &pdata->max_qos_steps);
struct s5p_mfc_platdata {
int ip_ver;
int debug_mode;
+ int nal_q;
#ifdef CONFIG_MFC_USE_BUS_DEVFREQ
int num_qos_steps;
int max_qos_steps;
};
/************************ NAL_Q data structure ************************/
-#define NAL_Q_ENABLE 1
-
#define NAL_Q_IN_ENTRY_SIZE 256
#define NAL_Q_OUT_ENTRY_SIZE 256
mutex_unlock(&dev->hwlock_wq.wait_mutex);
}
-#ifdef NAL_Q_ENABLE
/* Stop NAL-Q after getting hwlock */
if (dev->nal_q_handle)
s5p_mfc_nal_q_stop_if_started(dev);
-#endif
+
return 0;
}
mutex_unlock(&curr_ctx->hwlock_wq.wait_mutex);
}
-#ifdef NAL_Q_ENABLE
/* Stop NAL-Q after getting hwlock */
if (dev->nal_q_handle)
s5p_mfc_nal_q_stop_if_started(dev);
-#endif
+
return 0;
}
s5p_mfc_pm_clock_on_with_base(dev, (is_drm ? MFCBUF_DRM : MFCBUF_NORMAL));
}
-#ifdef NAL_Q_ENABLE
/*
* Return value description
* 0: NAL-Q is handled successfully
return ret;
}
-#endif
static int mfc_just_run_dec(struct s5p_mfc_ctx *ctx)
{
mfc_debug(2, "need_cache_flush = %d, is_drm = %d\n", need_cache_flush, ctx->is_drm);
-#ifdef NAL_Q_ENABLE
if (dev->nal_q_handle) {
ret = mfc_nal_q_just_run(ctx, need_cache_flush);
if (ret == 0) {
return ret;
}
}
-#endif
+
mfc_debug(2, "continue_clock_on = %d\n", dev->continue_clock_on);
if (!dev->continue_clock_on) {
s5p_mfc_pm_clock_on(dev);
return IRQ_WAKE_THREAD;
}
-#ifdef NAL_Q_ENABLE
/*
* Return value description
* 0: NAL-Q is handled successfully
return ret;
}
-#endif
static inline int mfc_handle_done_frame(struct s5p_mfc_ctx *ctx,
unsigned int reason, unsigned int err)
if (is_err_condition(err))
call_dop(dev, dump_and_stop_debug_mode, dev);
-#ifdef NAL_Q_ENABLE
if (dev->nal_q_handle) {
ret = mfc_nal_q_irq(dev, reason, err);
if (ret == 0) {
goto irq_end;
}
}
-#endif
ret = mfc_irq_dev(dev, reason, err);
if (!ret)
#include "s5p_mfc_buf.h"
#include "s5p_mfc_mem.h"
-#ifdef NAL_Q_ENABLE
#define CBR_I_LIMIT_MAX 5
int s5p_mfc_nal_q_check_enable(struct s5p_mfc_dev *dev)
{
MFC_WRITEL(pStr->PictureTimeBot, S5P_FIMV_D_RET_PICTURE_TIME_BOT); // 0xF680
}
#endif
-#endif