drm/i915/skl: Gen9 coarse power gating

Enable coarse power gating for Gen9. This feature allows render and
media engine to enter RC6 independently. Policies are configured
together with RC6. This feature will only be enabled when RC6 is
enabled.

v2: Rebase after Chris'/Mika's forcewake change (Damien)

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhe Wang <zhe1.wang@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dcb1b342cb979f5b8d9356eb91e5c54e2ecefd0..6f6de8929fd34885a461efa5b2d08728b8fbe80a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6072,6 +6072,9 @@ enum punit_power_well {
 #define GEN6_PMINTRMSK                         0xA168
 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP       (1<<31)
 #define VLV_PWRDWNUPCTL                                0xA294
+#define GEN9_MEDIA_PG_IDLE_HYSTERESIS          0xA0C4
+#define GEN9_RENDER_PG_IDLE_HYSTERESIS         0xA0C8
+#define GEN9_PG_ENABLE                         0xA210
 
 #define VLV_CHICKEN_3                          (VLV_DISPLAY_BASE + 0x7040C)
 #define  PIXEL_OVERLAP_CNT_MASK                        (3 << 30)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ae8e4ddb1c560e1c135e59d0d6b10808a60e238..4f7a2a52feefa33d733586c59e3d6588ddecf920 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3891,6 +3891,7 @@ static void gen9_disable_rps(struct drm_device *dev)
        struct drm_i915_private *dev_priv = dev->dev_private;
 
        I915_WRITE(GEN6_RC_CONTROL, 0);
+       I915_WRITE(GEN9_PG_ENABLE, 0);
 }
 
 static void gen6_disable_rps(struct drm_device *dev)
@@ -4080,6 +4081,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
        I915_WRITE(GEN6_RC_SLEEP, 0);
        I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
 
+       /* 2c: Program Coarse Power Gating Policies. */
+       I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
+       I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
+
        /* 3a: Enable RC6 */
        if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
                rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
@@ -4089,6 +4094,9 @@ static void gen9_enable_rc6(struct drm_device *dev)
                                   GEN6_RC_CTL_EI_MODE(1) |
                                   rc6_mask);
 
+       /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+       I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
+
        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
 }