s3fb: fix 15/16bpp modes with over 115MHz pixclocks on 86C365 Trio3D

Enable pixel multiplexing in 15/16bpp modes when pixclock is over 115MHz
on Trio3D (86C365) cards to fix artifacts on the left side of screen.

Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
Acked-by: Ondrej Zajicek <santiago@crfreenet.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c
index be12145681f6a87ab9653718921fde53767dd1a4..7b8fdc6d9d55a3a8a35752153b4301cdef32d2d1 100644 (file)
--- a/drivers/video/s3fb.c
+++ b/drivers/video/s3fb.c
@@ -675,6 +675,15 @@ static int s3fb_set_par(struct fb_info *info)
                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
                        else
                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
+               } else if (par->chip == CHIP_365_TRIO3D) {
+                       svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
+                       if (info->var.pixclock > 8695) {
+                               svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
+                               hmul = 2;
+                       } else {
+                               svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
+                               multiplex = 1;
+                       }
                } else {
                        svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
                        svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
@@ -691,6 +700,15 @@ static int s3fb_set_par(struct fb_info *info)
                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
                        else
                                svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
+               } else if (par->chip == CHIP_365_TRIO3D) {
+                       svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
+                       if (info->var.pixclock > 8695) {
+                               svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
+                               hmul = 2;
+                       } else {
+                               svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
+                               multiplex = 1;
+                       }
                } else {
                        svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
                        svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);