ath9k_hw: Fix enabling of MCI and RTT
authorMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Fri, 9 Mar 2012 06:31:55 +0000 (12:01 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 12 Mar 2012 18:19:37 +0000 (14:19 -0400)
tested in AR9462 Rev:2, both hardware capability flag are set

Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/reg.h

index d582cf73098fec9b06595babeaa2036c3ad6992b..02cc1ce3dd6a22d87b35b67a8cb3c3e5d815ee7c 100644 (file)
@@ -2390,8 +2390,17 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                if (AR_SREV_9485_OR_LATER(ah))
                        ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
        }
-       if (AR_SREV_9462(ah))
-               pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI;
+
+       if (AR_SREV_9462(ah)) {
+
+               if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
+                       pCap->hw_caps |= ATH9K_HW_CAP_MCI;
+
+               if (AR_SREV_9462_20(ah))
+                       pCap->hw_caps |= ATH9K_HW_CAP_RTT;
+
+       }
+
 
        return 0;
 }
index 80b1856f817deff8522ef0c32aee21d9b57c1de8..458f81b4a7cb7406d3e98f0c7d455cec93206749 100644 (file)
@@ -1151,6 +1151,7 @@ enum {
 #define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
 #define AR_ENT_OTP               0x40d8
 #define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
+#define AR_ENT_OTP_49GHZ_DISABLE               0x00100000
 #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE                0x00800000
 
 #define AR_CH0_BB_DPLL1                 0x16180