--- /dev/null
+/*
+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos9610 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <soc/samsung/cal-if.h>
+#include <dt-bindings/clock/exynos9610.h>
+
+#include "../../soc/samsung/cal-if/exynos9610/cmucal-vclk.h"
+#include "../../soc/samsung/cal-if/exynos9610/cmucal-node.h"
+#include "../../soc/samsung/cal-if/exynos9610/cmucal-qch.h"
+#include "../../soc/samsung/cal-if/exynos9610/clkout_exynos9610.h"
+#include "composite.h"
+
+static struct samsung_clk_provider *exynos9610_clk_provider;
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate exynos9610_fixed_rate_ext_clks[] __initdata = {
+ FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
+};
+
+/* HWACG VCLK */
+struct init_vclk exynos9610_apm_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS_USER, "UMUX_CLKCMU_APM_BUS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBEINTEGRATION_QCH_GREBE", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBEINTEGRATION_QCH_DBG", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_INTMEM_QCH, INTMEM_QCH, "GATE_INTMEM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP_QCH, MAILBOX_AP2CP_QCH, "GATE_MAILBOX_AP2CP_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP_S_QCH, MAILBOX_AP2CP_S_QCH, "GATE_MAILBOX_AP2CP_S_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2GNSS_QCH, MAILBOX_AP2GNSS_QCH, "GATE_MAILBOX_AP2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2SHUB_QCH, MAILBOX_AP2SHUB_QCH, "GATE_MAILBOX_AP2SHUB_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2WLBT_QCH, MAILBOX_AP2WLBT_QCH, "GATE_MAILBOX_AP2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2AP_QCH, MAILBOX_APM2AP_QCH, "GATE_MAILBOX_APM2AP_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2CP_QCH, MAILBOX_APM2CP_QCH, "GATE_MAILBOX_APM2CP_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2GNSS_QCH, MAILBOX_APM2GNSS_QCH, "GATE_MAILBOX_APM2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2SHUB_QCH, MAILBOX_APM2SHUB_QCH, "GATE_MAILBOX_APM2SHUB_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2WLBT_QCH, MAILBOX_APM2WLBT_QCH, "GATE_MAILBOX_APM2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CP2GNSS_QCH, MAILBOX_CP2GNSS_QCH, "GATE_MAILBOX_CP2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CP2SHUB_QCH, MAILBOX_CP2SHUB_QCH, "GATE_MAILBOX_CP2SHUB_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CP2WLBT_QCH, MAILBOX_CP2WLBT_QCH, "GATE_MAILBOX_CP2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_SHUB2GNSS_QCH, MAILBOX_SHUB2GNSS_QCH, "GATE_MAILBOX_SHUB2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_SHUB2WLBT_QCH, MAILBOX_SHUB2WLBT_QCH, "GATE_MAILBOX_SHUB2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_WLBT2ABOX_QCH, MAILBOX_WLBT2ABOX_QCH, "GATE_MAILBOX_WLBT2ABOX_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_WLBT2GNSS_QCH, MAILBOX_WLBT2GNSS_QCH, "GATE_MAILBOX_WLBT2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PEM_QCH, PEM_QCH, "GATE_PEM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_APM_QCH, SPEEDY_APM_QCH, "GATE_SPEEDY_APM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_APM_QCH, SYSREG_APM_QCH, "GATE_SYSREG_APM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_APM_QCH, WDT_APM_QCH, "GATE_WDT_APM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_cam_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_CAM_BUS, MUX_CLKCMU_CAM_BUS_USER, "UMUX_CLKCMU_CAM_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0, IS6P10P0_CAM_QCH_S_CAM_CSIS0, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1, IS6P10P0_CAM_QCH_S_CAM_CSIS1, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2, IS6P10P0_CAM_QCH_S_CAM_CSIS2, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3, IS6P10P0_CAM_QCH_S_CAM_CSIS3, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_3AA, IS6P10P0_CAM_QCH_S_CAM_3AA, "GATE_IS6P10P0_CAM_QCH_S_CAM_3AA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU, IS6P10P0_CAM_QCH_S_CAM_SMMU, "GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE, IS6P10P0_CAM_QCH_S_CAM_PDP_CORE, "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA, IS6P10P0_CAM_QCH_S_CAM_PDP_DMA, "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA, IS6P10P0_CAM_QCH_S_CAM_RDMA, "GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_cmgp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(MUX_CMGP_ADC, MUX_CLK_CMGP_ADC, "MUX_CMGP_ADC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_I2C, MUX_CLK_CMGP_I2C, "MUX_CMGP_I2C", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI00, MUX_CLK_CMGP_USI00, "MUX_CMGP_USI00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI01, MUX_CLK_CMGP_USI01, "MUX_CMGP_USI01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI02, MUX_CLK_CMGP_USI02, "MUX_CMGP_USI02", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI03, MUX_CLK_CMGP_USI03, "MUX_CMGP_USI03", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI04, MUX_CLK_CMGP_USI04, "MUX_CMGP_USI04", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_QCH_S0, ADC_CMGP_QCH_S0, "GATE_ADC_CMGP_QCH_S0", "MUX_CMGP_ADC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_QCH_S1, ADC_CMGP_QCH_S1, "GATE_ADC_CMGP_QCH_S1", "MUX_CMGP_ADC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_QCH_ADC, ADC_CMGP_QCH_ADC, "GATE_ADC_CMGP_QCH_ADC", "MUX_CMGP_ADC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP00_QCH, I2C_CMGP00_QCH, "GATE_I2C_CMGP00_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP01_QCH, I2C_CMGP01_QCH, "GATE_I2C_CMGP01_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP02_QCH, I2C_CMGP02_QCH, "GATE_I2C_CMGP02_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP03_QCH, I2C_CMGP03_QCH, "GATE_I2C_CMGP03_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP04_QCH, I2C_CMGP04_QCH, "GATE_I2C_CMGP04_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP00_QCH, USI_CMGP00_QCH, "GATE_USI_CMGP00_QCH", "MUX_CMGP_USI00", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP01_QCH, USI_CMGP01_QCH, "GATE_USI_CMGP01_QCH", "MUX_CMGP_USI01", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP02_QCH, USI_CMGP02_QCH, "GATE_USI_CMGP02_QCH", "MUX_CMGP_USI02", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP03_QCH, USI_CMGP03_QCH, "GATE_USI_CMGP03_QCH", "MUX_CMGP_USI03", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP04_QCH, USI_CMGP04_QCH, "GATE_USI_CMGP04_QCH", "MUX_CMGP_USI04", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_top_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS0, DFTMUX_TOP_QCH_CLK_CSIS0, "GATE_DFTMUX_TOP_QCH_CLK_CSIS0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS1, DFTMUX_TOP_QCH_CLK_CSIS1, "GATE_DFTMUX_TOP_QCH_CLK_CSIS1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS2, DFTMUX_TOP_QCH_CLK_CSIS2, "GATE_DFTMUX_TOP_QCH_CLK_CSIS2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS3, DFTMUX_TOP_QCH_CLK_CSIS3, "GATE_DFTMUX_TOP_QCH_CLK_CSIS3", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_QCH, OTP_QCH, "GATE_OTP_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_core_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(MUX_CORE_GIC, MUX_CLK_CORE_GIC, "MUX_CORE_GIC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GIC400_AIHWACG_QCH, GIC400_AIHWACG_QCH, "GATE_GIC400_AIHWACG_QCH", "MUX_CORE_GIC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PDMA_CORE_QCH, PDMA_CORE_QCH, "GATE_PDMA_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW_CORE_MEM0_QCH, PPFW_CORE_MEM0_QCH, "GATE_PPFW_CORE_MEM0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW_CORE_MEM1_QCH, PPFW_CORE_MEM1_QCH, "GATE_PPFW_CORE_MEM1_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW_CORE_PERI_QCH, PPFW_CORE_PERI_QCH, "GATE_PPFW_CORE_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SIREX_QCH, SIREX_QCH, "GATE_SIREX_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPDMA_CORE_QCH, SPDMA_CORE_QCH, "GATE_SPDMA_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_D_CORE_QCH, TREX_D_CORE_QCH, "GATE_TREX_D_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_D_NRT_QCH, TREX_D_NRT_QCH, "GATE_TREX_D_NRT_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P_CORE_QCH, TREX_P_CORE_QCH, "GATE_TREX_P_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_dispaud_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(MUX_AUD_FM, MUX_CLK_AUD_FM, "MUX_AUD_FM", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_DISPAUD_BUS, MUX_CLKCMU_DISPAUD_DISP, "MUX_CLKCMU_DISPAUD_DISP", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_CPU, ABOX_QCH_CPU, "GATE_ABOX_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_ACLK, ABOX_QCH_S_ACLK, "GATE_ABOX_QCH_S_ACLK", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK0, ABOX_QCH_S_BCLK0, "GATE_ABOX_QCH_S_BCLK0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK2, ABOX_QCH_S_BCLK2, "GATE_ABOX_QCH_S_BCLK2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK1, ABOX_QCH_S_BCLK1, "GATE_ABOX_QCH_S_BCLK1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_FM, ABOX_QCH_FM, "GATE_ABOX_QCH_FM", "MUX_AUD_FM", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK_DSIF, ABOX_QCH_S_BCLK_DSIF, "GATE_ABOX_QCH_S_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_QCH_S_DPP, DPU_QCH_S_DPP, "GATE_DPU_QCH_S_DPP", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_QCH_S_DMA, DPU_QCH_S_DMA, "GATE_DPU_QCH_S_DMA", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_QCH_S_DECON, DPU_QCH_S_DECON, "GATE_DPU_QCH_S_DECON", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_ABOX_QCH, SMMU_ABOX_QCH, "GATE_SMMU_ABOX_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_DPU_QCH, SMMU_DPU_QCH, "GATE_SMMU_DPU_QCH", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_AUD_QCH, WDT_AUD_QCH, "GATE_WDT_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_fsys_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_BUS, MUX_CLKCMU_FSYS_BUS_USER, "MUX_CLKCMU_FSYS_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_MMC_EMBD, MUX_CLKCMU_FSYS_MMC_EMBD_USER, "MUX_CLKCMU_FSYS_MMC_EMBD_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_MMC_CARD, MUX_CLKCMU_FSYS_MMC_CARD_USER, "MUX_CLKCMU_FSYS_MMC_CARD_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_UFS_EMBD, MUX_CLKCMU_FSYS_UFS_EMBD_USER, "MUX_CLKCMU_FSYS_UFS_EMBD_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_MMC_CARD_QCH, MMC_CARD_QCH, "GATE_MMC_CARD_QCH", "MUX_CLKCMU_FSYS_MMC_CARD_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MMC_EMBD_QCH, MMC_EMBD_QCH, "GATE_MMC_EMBD_QCH", "MUX_CLKCMU_FSYS_MMC_EMBD_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_RTIC_QCH, RTIC_QCH, "GATE_RTIC_QCH", "MUX_CLKCMU_FSYS_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SSS_QCH, SSS_QCH, "GATE_SSS_QCH", "MUX_CLKCMU_FSYS_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD_QCH_UFS, UFS_EMBD_QCH_UFS, "GATE_UFS_EMBD_QCH_UFS", "MUX_CLKCMU_FSYS_UFS_EMBD_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD_QCH_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_QCH_FMP", "MUX_CLKCMU_FSYS_UFS_EMBD_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_g2d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, "MUX_CLKCMU_G2D_G2D_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL_USER, "MUX_CLKCMU_G2D_MSCL_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_G2D_QCH, G2D_QCH, "GATE_G2D_QCH", "MUX_CLKCMU_G2D_G2D_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_JPEG_QCH, JPEG_QCH, "GATE_JPEG_QCH", "MUX_CLKCMU_G2D_MSCL_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MSCL_QCH, MSCL_QCH, "GATE_MSCL_QCH", "MUX_CLKCMU_G2D_MSCL_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_G2D_QCH, SYSMMU_G2D_QCH, "GATE_SYSMMU_G2D_QCH", "MUX_CLKCMU_G2D_G2D_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_g3d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_G3D_QCH, G3D_QCH, "GATE_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_isp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISP_BUS, MUX_CLKCMU_ISP_BUS_USER, "MUX_CLKCMU_ISP_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISP_GDC, MUX_CLKCMU_ISP_GDC_USER, "MUX_CLKCMU_ISP_GDC_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISP_VRA, MUX_CLKCMU_ISP_VRA_USER, "MUX_CLKCMU_ISP_VRA_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_ISP, IS6P10P0_ISP_QCH_S_ISP_ISP, "GATE_IS6P10P0_ISP_QCH_S_ISP_ISP", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC, IS6P10P0_ISP_QCH_S_ISP_MCSC, "GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_VRA, IS6P10P0_ISP_QCH_S_ISP_VRA, "GATE_IS6P10P0_ISP_QCH_S_ISP_VRA", "MUX_CLKCMU_ISP_VRA_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_GDC, IS6P10P0_ISP_QCH_S_ISP_GDC, "GATE_IS6P10P0_ISP_QCH_S_ISP_GDC", "MUX_CLKCMU_ISP_GDC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0, IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0, "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1, IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1, "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_mfc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_MFC_MFC, MUX_CLKCMU_MFC_MFC_USER, "MUX_CLKCMU_MFC_MFC_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD_USER, "MUX_CLKCMU_MFC_WFD_USER", "MUX_CLKCMU_MFC_MFC_USER", 0, 0, NULL),
+ HWACG_VCLK(GATE_MFC_QCH, MFC_QCH, "GATE_MFC_QCH", "MUX_CLKCMU_MFC_MFC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_MFCD0_QCH, SYSMMU_MFCD0_QCH, "GATE_SYSMMU_MFCD0_QCH", "MUX_CLKCMU_MFC_MFC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_MFCD1_QCH, SYSMMU_MFCD1_QCH, "GATE_SYSMMU_MFCD1_QCH", "MUX_CLKCMU_MFC_MFC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WFD_QCH, WFD_QCH, "GATE_WFD_QCH", "MUX_CLKCMU_MFC_WFD_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_peri_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERI_UART, MUX_CLKCMU_PERI_UART_USER, "UMUX_CLKCMU_PERI_UART", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_0_QCH, CAMI2C_0_QCH, "GATE_CAMI2C_0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_1_QCH, CAMI2C_1_QCH, "GATE_CAMI2C_1_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_2_QCH, CAMI2C_2_QCH, "GATE_CAMI2C_2_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_3_QCH, CAMI2C_3_QCH, "GATE_CAMI2C_3_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_0_QCH, I2C_0_QCH, "GATE_I2C_0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_1_QCH, I2C_1_QCH, "GATE_I2C_1_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_2_QCH, I2C_2_QCH, "GATE_I2C_2_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_3_QCH, I2C_3_QCH, "GATE_I2C_3_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_4_QCH, I2C_4_QCH, "GATE_I2C_4_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_5_QCH, I2C_5_QCH, "GATE_I2C_5_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_6_QCH, I2C_6_QCH, "GATE_I2C_6_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MCT_QCH, MCT_QCH, "GATE_MCT_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_TOP_QCH, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PWM_MOTOR_QCH, PWM_MOTOR_QCH, "GATE_PWM_MOTOR_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_0_QCH, SPI_0_QCH, "GATE_SPI_0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_1_QCH, SPI_1_QCH, "GATE_SPI_1_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_2_QCH, SPI_2_QCH, "GATE_SPI_2_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_QCH, UART_QCH, "GATE_UART_QCH", "UMUX_CLKCMU_PERI_UART", 0, 0, "console-pclk0"),
+ HWACG_VCLK(GATE_USI00_I2C_QCH, USI00_I2C_QCH, "GATE_USI00_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI00_USI_QCH, USI00_USI_QCH, "GATE_USI00_USI_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER0_QCH, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER1_QCH, WDT_CLUSTER1_QCH, "GATE_WDT_CLUSTER1_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_shub_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_SHUB_BUS, MUX_CLKCMU_SHUB_BUS_USER, "MUX_CLKCMU_SHUB_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(MUX_SHUB_I2C, MUX_CLK_SHUB_I2C, "MUX_SHUB_I2C", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_SHUB_USI00, MUX_CLK_SHUB_USI00, "MUX_SHUB_USI00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_SHUB_USI01, MUX_CLK_SHUB_USI01, "MUX_SHUB_USI01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CM4_SHUB_QCH, CM4_SHUB_QCH, "GATE_CM4_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_SHUB00_QCH, I2C_SHUB00_QCH, "GATE_I2C_SHUB00_QCH", "MUX_SHUB_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PDMA_SHUB_QCH, PDMA_SHUB_QCH, "GATE_PDMA_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PWM_SHUB_QCH, PWM_SHUB_QCH, "GATE_PWM_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TIMER_SHUB_QCH, TIMER_SHUB_QCH, "GATE_TIMER_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_SHUB00_QCH, USI_SHUB00_QCH, "GATE_USI_SHUB00_QCH", "MUX_SHUB_USI00", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_SHUB_QCH, WDT_SHUB_QCH, "GATE_WDT_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_usb_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_USB_USBDRD30, MUX_CLKCMU_USB_USB30DRD, "MUX_CLKCMU_USB_USB30DRD", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_USB_DPGTC, MUX_CLKCMU_USB_DPGTC, "MUX_CLKCMU_USB_DPGTC", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_DP_LINK_QCH_DP, DP_LINK_QCH_DP, "GATE_DP_LINK_QCH_DP", "MUX_CLKCMU_USB_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DP_LINK_QCH_GTC, DP_LINK_QCH_GTC, "GATE_DP_LINK_QCH_GTC", "MUX_CLKCMU_USB_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USB30, USB30DRD_QCH_USB30, "GATE_USB30DRD_QCH_USB30", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USBPHY_30CTRL_0, USB30DRD_QCH_USBPHY_30CTRL_0, "GATE_USB30DRD_QCH_USBPHY_30CTRL_0", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USBPHY_30CTRL_1, USB30DRD_QCH_USBPHY_30CTRL_1, "GATE_USB30DRD_QCH_USBPHY_30CTRL_1", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USBPHY_20CTRL, USB30DRD_QCH_USBPHY_20CTRL, "GATE_USB30DRD_QCH_USBPHY_20CTRL", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_vipx1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_VIPX1_BUS, MUX_CLKCMU_VIPX1_BUS_USER, "MUX_CLKCMU_VIPX1_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_SMMU_D_VIPX1_QCH, SMMU_D_VIPX1_QCH, "GATE_SMMU_D_VIPX1_QCH", "MUX_CLKCMU_VIPX1_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VIPX1_QCH, VIPX1_QCH, "GATE_VIPX1_QCH", "MUX_CLKCMU_VIPX1_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_vipx2_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_VIPX2_BUS, MUX_CLKCMU_VIPX2_BUS_USER, "MUX_CLKCMU_VIPX2_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_SMMU_D_VIPX2_QCH, SMMU_D_VIPX2_QCH, "GATE_SMMU_D_VIPX2_QCH", "MUX_CLKCMU_VIPX2_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VIPX2_QCH, VIPX2_QCH, "GATE_VIPX2_QCH", "MUX_CLKCMU_VIPX2_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VIPX2_QCH_LOCAL, VIPX2_QCH_LOCAL, "GATE_VIPX2_QCH_LOCAL", "MUX_CLKCMU_VIPX2_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+/* Special VCLK */
+struct init_vclk exynos9610_dispaud_vclks[] __initdata = {
+ VCLK(DOUT_CLK_AUD_ACLK, DIV_CLK_AUD_BUS, "DOUT_CLK_AUD_ACLK", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_CLK_AUD_AUDIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_DSIF, DIV_CLK_AUD_DSIF, "DOUT_CLK_AUD_DSIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_CLK_AUD_UAIF0", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_CLK_AUD_UAIF1", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_CLK_AUD_UAIF2", 0, 0, NULL),
+ VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_cmgp_vclks[] __initdata = {
+ VCLK(CMGP00_USI, DIV_CLK_CMGP_USI00, "CMGP00_USI", 0, 0, NULL),
+ VCLK(CMGP01_USI, DIV_CLK_CMGP_USI01, "CMGP01_USI", 0, 0, NULL),
+ VCLK(CMGP02_USI, DIV_CLK_CMGP_USI02, "CMGP02_USI", 0, 0, NULL),
+ VCLK(CMGP03_USI, DIV_CLK_CMGP_USI03, "CMGP03_USI", 0, 0, NULL),
+ VCLK(CMGP04_USI, DIV_CLK_CMGP_USI04, "CMGP04_USI", 0, 0, NULL),
+ VCLK(CMGP_I2C, DIV_CLK_CMGP_I2C, "CMGP_I2C", 0, 0, NULL),
+ VCLK(CMGP_ADC, DIV_CLK_CMGP_ADC, "CMGP_ADC", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_fsys_vclks[] __initdata = {
+ VCLK(MMC_EMBD, CLKCMU_FSYS_MMC_EMBD, "MMC_EMBD", 0, 0, NULL),
+ VCLK(MMC_CARD, CLKCMU_FSYS_MMC_CARD, "MMC_CARD", 0, 0, NULL),
+ VCLK(UFS_EMBD, CLKCMU_FSYS_UFS_EMBD, "UFS_EMBD", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_usb_vclks[] __initdata = {
+ VCLK(USB30DRD, VCLK_CLKCMU_USB_USB30DRD, "USB30DRD", 0, 0, NULL),
+ VCLK(DP_LINK, VCLK_CLKCMU_USB_DPGTC, "DP_LINK", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_peri_vclks[] __initdata = {
+ VCLK(UART, CLKCMU_PERI_UART, "UART", 0, 0, "console-sclk0"),
+ VCLK(I2C, DIV_CLK_PERI_I2C, "I2C", 0, 0, NULL),
+ VCLK(SPI0, DIV_CLK_PERI_SPI0, "SPI0", 0, 0, NULL),
+ VCLK(SPI1, DIV_CLK_PERI_SPI1, "SPI1", 0, 0, NULL),
+ VCLK(SPI2, DIV_CLK_PERI_SPI2, "SPI2", 0, 0, NULL),
+ VCLK(USI_I2C, DIV_CLK_PERI_USI_I2C, "USI_I2C", 0, 0, NULL),
+ VCLK(USI_USI, DIV_CLK_PERI_USI_USI, "USI_USI", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_top_vclks[] __initdata = {
+ VCLK(CIS_CLK0, CLKCMU_CIS_CLK0, "CIS_CLK0", 0, 0, NULL),
+ VCLK(CIS_CLK1, CLKCMU_CIS_CLK1, "CIS_CLK1", 0, 0, NULL),
+ VCLK(CIS_CLK2, CLKCMU_CIS_CLK2, "CIS_CLK2", 0, 0, NULL),
+ VCLK(CIS_CLK3, CLKCMU_CIS_CLK3, "CIS_CLK3", 0, 0, NULL),
+};
+
+static struct init_vclk exynos9610_clkout_vclks[] __initdata = {
+ VCLK(OSC_NFC, VCLK_CLKOUT1, "OSC_NFC", 0, 0, NULL),
+ VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ {.compatible = "samsung,exynos9610-oscclk", .data = (void *)0},
+ {},
+};
+
+void exynos9610_vclk_init(void)
+{
+ /* Common clock init */
+}
+
+/* register exynos9610 clocks */
+void __init exynos9610_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ int ret;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ ret = cal_if_init(np);
+ if (ret)
+ panic("%s: unable to initialize cal-if\n", __func__);
+
+ exynos9610_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (!exynos9610_clk_provider)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_register_of_fixed_ext(exynos9610_clk_provider, exynos9610_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos9610_fixed_rate_ext_clks),
+ ext_clk_match);
+ /* register HWACG vclk */
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_apm_hwacg_vclks, ARRAY_SIZE(exynos9610_apm_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_cam_hwacg_vclks, ARRAY_SIZE(exynos9610_cam_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_cmgp_hwacg_vclks, ARRAY_SIZE(exynos9610_cmgp_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_top_hwacg_vclks, ARRAY_SIZE(exynos9610_top_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_core_hwacg_vclks, ARRAY_SIZE(exynos9610_core_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_dispaud_hwacg_vclks, ARRAY_SIZE(exynos9610_dispaud_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_fsys_hwacg_vclks, ARRAY_SIZE(exynos9610_fsys_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_g2d_hwacg_vclks, ARRAY_SIZE(exynos9610_g2d_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_g3d_hwacg_vclks, ARRAY_SIZE(exynos9610_g3d_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_isp_hwacg_vclks, ARRAY_SIZE(exynos9610_isp_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_mfc_hwacg_vclks, ARRAY_SIZE(exynos9610_mfc_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_peri_hwacg_vclks, ARRAY_SIZE(exynos9610_peri_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_shub_hwacg_vclks, ARRAY_SIZE(exynos9610_shub_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_usb_hwacg_vclks, ARRAY_SIZE(exynos9610_usb_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_vipx1_hwacg_vclks, ARRAY_SIZE(exynos9610_vipx1_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_vipx2_hwacg_vclks, ARRAY_SIZE(exynos9610_vipx2_hwacg_vclks));
+
+ /* register special vclk */
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_dispaud_vclks, ARRAY_SIZE(exynos9610_dispaud_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_cmgp_vclks, ARRAY_SIZE(exynos9610_cmgp_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_fsys_vclks, ARRAY_SIZE(exynos9610_fsys_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_usb_vclks, ARRAY_SIZE(exynos9610_usb_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_peri_vclks, ARRAY_SIZE(exynos9610_peri_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_top_vclks, ARRAY_SIZE(exynos9610_top_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_clkout_vclks, ARRAY_SIZE(exynos9610_clkout_vclks));
+
+ clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);
+
+ samsung_clk_of_add_provider(np, exynos9610_clk_provider);
+
+ late_time_init = exynos9610_vclk_init;
+
+ pr_info("EXYNOS9610: Clock setup completed\n");
+}
+
+CLK_OF_DECLARE(exynos9610_clk, "samsung,exynos9610-clock", exynos9610_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos9610 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_9610_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_9610_H
+
+#define NONE (0 + 0)
+#define OSCCLK (0 + 1)
+
+/* NUMBER FOR APM DRIVER STARTS FROM 10 */
+#define CLK_APM_BASE (10)
+#define UMUX_CLKCMU_APM_BUS (CLK_APM_BASE + 0)
+#define GATE_GREBEINTEGRATION_QCH_GREBE (CLK_APM_BASE + 1)
+#define GATE_GREBEINTEGRATION_QCH_DBG (CLK_APM_BASE + 2)
+#define GATE_INTMEM_QCH (CLK_APM_BASE + 3)
+#define GATE_MAILBOX_AP2CP_QCH (CLK_APM_BASE + 4)
+#define GATE_MAILBOX_AP2CP_S_QCH (CLK_APM_BASE + 5)
+#define GATE_MAILBOX_AP2GNSS_QCH (CLK_APM_BASE + 6)
+#define GATE_MAILBOX_AP2SHUB_QCH (CLK_APM_BASE + 7)
+#define GATE_MAILBOX_AP2WLBT_QCH (CLK_APM_BASE + 8)
+#define GATE_MAILBOX_APM2AP_QCH (CLK_APM_BASE + 9)
+#define GATE_MAILBOX_APM2CP_QCH (CLK_APM_BASE + 10)
+#define GATE_MAILBOX_APM2GNSS_QCH (CLK_APM_BASE + 11)
+#define GATE_MAILBOX_APM2SHUB_QCH (CLK_APM_BASE + 12)
+#define GATE_MAILBOX_APM2WLBT_QCH (CLK_APM_BASE + 13)
+#define GATE_MAILBOX_CP2GNSS_QCH (CLK_APM_BASE + 14)
+#define GATE_MAILBOX_CP2SHUB_QCH (CLK_APM_BASE + 15)
+#define GATE_MAILBOX_CP2WLBT_QCH (CLK_APM_BASE + 16)
+#define GATE_MAILBOX_SHUB2GNSS_QCH (CLK_APM_BASE + 17)
+#define GATE_MAILBOX_SHUB2WLBT_QCH (CLK_APM_BASE + 18)
+#define GATE_MAILBOX_WLBT2ABOX_QCH (CLK_APM_BASE + 19)
+#define GATE_MAILBOX_WLBT2GNSS_QCH (CLK_APM_BASE + 20)
+#define GATE_PEM_QCH (CLK_APM_BASE + 21)
+#define GATE_SPEEDY_APM_QCH (CLK_APM_BASE + 22)
+#define GATE_SYSREG_APM_QCH (CLK_APM_BASE + 23)
+#define GATE_WDT_APM_QCH (CLK_APM_BASE + 24)
+
+/* NUMBER FOR CAM DRIVER STARTS FROM 40 */
+#define CLK_CAM_BASE (40)
+#define UMUX_CLKCMU_CAM_BUS (CLK_CAM_BASE + 0)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0 (CLK_CAM_BASE + 1)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1 (CLK_CAM_BASE + 2)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2 (CLK_CAM_BASE + 3)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3 (CLK_CAM_BASE + 4)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_3AA (CLK_CAM_BASE + 5)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU (CLK_CAM_BASE + 6)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE (CLK_CAM_BASE + 7)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA (CLK_CAM_BASE + 8)
+#define GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA (CLK_CAM_BASE + 9)
+
+/* NUMBER FOR CMGP DRIVER STARTS FROM 100 */
+#define CLK_CMGP_BASE (100)
+#define MUX_CMGP_ADC (CLK_CMGP_BASE + 0)
+#define MUX_CMGP_I2C (CLK_CMGP_BASE + 1)
+#define MUX_CMGP_USI00 (CLK_CMGP_BASE + 2)
+#define MUX_CMGP_USI01 (CLK_CMGP_BASE + 3)
+#define MUX_CMGP_USI02 (CLK_CMGP_BASE + 4)
+#define MUX_CMGP_USI03 (CLK_CMGP_BASE + 5)
+#define MUX_CMGP_USI04 (CLK_CMGP_BASE + 6)
+#define GATE_ADC_CMGP_QCH_S0 (CLK_CMGP_BASE + 7)
+#define GATE_ADC_CMGP_QCH_S1 (CLK_CMGP_BASE + 8)
+#define GATE_ADC_CMGP_QCH_ADC (CLK_CMGP_BASE + 9)
+#define GATE_I2C_CMGP00_QCH (CLK_CMGP_BASE + 10)
+#define GATE_I2C_CMGP01_QCH (CLK_CMGP_BASE + 11)
+#define GATE_I2C_CMGP02_QCH (CLK_CMGP_BASE + 12)
+#define GATE_I2C_CMGP03_QCH (CLK_CMGP_BASE + 13)
+#define GATE_I2C_CMGP04_QCH (CLK_CMGP_BASE + 14)
+#define GATE_USI_CMGP00_QCH (CLK_CMGP_BASE + 15)
+#define GATE_USI_CMGP01_QCH (CLK_CMGP_BASE + 16)
+#define GATE_USI_CMGP02_QCH (CLK_CMGP_BASE + 17)
+#define GATE_USI_CMGP03_QCH (CLK_CMGP_BASE + 18)
+#define GATE_USI_CMGP04_QCH (CLK_CMGP_BASE + 19)
+#define CMGP00_USI (CLK_CMGP_BASE + 20)
+#define CMGP01_USI (CLK_CMGP_BASE + 21)
+#define CMGP02_USI (CLK_CMGP_BASE + 22)
+#define CMGP03_USI (CLK_CMGP_BASE + 23)
+#define CMGP04_USI (CLK_CMGP_BASE + 24)
+#define CMGP_I2C (CLK_CMGP_BASE + 25)
+#define CMGP_ADC (CLK_CMGP_BASE + 26)
+
+/* NUMBER FOR TOP DRIVER STARTS FROM 150 */
+#define CLK_TOP_BASE (150)
+#define GATE_DFTMUX_TOP_QCH_CLK_CSIS0 (CLK_TOP_BASE + 0)
+#define GATE_DFTMUX_TOP_QCH_CLK_CSIS1 (CLK_TOP_BASE + 1)
+#define GATE_DFTMUX_TOP_QCH_CLK_CSIS2 (CLK_TOP_BASE + 2)
+#define GATE_DFTMUX_TOP_QCH_CLK_CSIS3 (CLK_TOP_BASE + 3)
+#define GATE_OTP_QCH (CLK_TOP_BASE + 4)
+#define CIS_CLK0 (CLK_TOP_BASE + 5)
+#define CIS_CLK1 (CLK_TOP_BASE + 6)
+#define CIS_CLK2 (CLK_TOP_BASE + 7)
+#define CIS_CLK3 (CLK_TOP_BASE + 8)
+
+/* NUMBER FOR CORE DRIVER STARTS FROM 200 */
+#define CLK_CORE_BASE (200)
+#define MUX_CORE_GIC (CLK_CORE_BASE + 0)
+#define GATE_GIC400_AIHWACG_QCH (CLK_CORE_BASE + 1)
+#define GATE_PDMA_CORE_QCH (CLK_CORE_BASE + 2)
+#define GATE_PPFW_CORE_MEM0_QCH (CLK_CORE_BASE + 3)
+#define GATE_PPFW_CORE_MEM1_QCH (CLK_CORE_BASE + 4)
+#define GATE_PPFW_CORE_PERI_QCH (CLK_CORE_BASE + 5)
+#define GATE_SIREX_QCH (CLK_CORE_BASE + 6)
+#define GATE_SPDMA_CORE_QCH (CLK_CORE_BASE + 7)
+#define GATE_TREX_D_CORE_QCH (CLK_CORE_BASE + 8)
+#define GATE_TREX_D_NRT_QCH (CLK_CORE_BASE + 9)
+#define GATE_TREX_P_CORE_QCH (CLK_CORE_BASE + 10)
+
+/* NUMBER FOR DISPAUD DRIVER STARTS FROM 250 */
+#define CLK_DISPAUD_BASE (250)
+#define MUX_AUD_FM (CLK_DISPAUD_BASE + 0)
+#define UMUX_CLKCMU_DISPAUD_BUS (CLK_DISPAUD_BASE + 1)
+#define GATE_ABOX_QCH_CPU (CLK_DISPAUD_BASE + 2)
+#define GATE_ABOX_QCH_S_ACLK (CLK_DISPAUD_BASE + 3)
+#define GATE_ABOX_QCH_S_BCLK0 (CLK_DISPAUD_BASE + 4)
+#define GATE_ABOX_QCH_S_BCLK2 (CLK_DISPAUD_BASE + 5)
+#define GATE_ABOX_QCH_S_BCLK1 (CLK_DISPAUD_BASE + 6)
+#define GATE_ABOX_QCH_FM (CLK_DISPAUD_BASE + 7)
+#define GATE_ABOX_QCH_S_BCLK_DSIF (CLK_DISPAUD_BASE + 8)
+#define GATE_DPU_QCH_S_DPP (CLK_DISPAUD_BASE + 9)
+#define GATE_DPU_QCH_S_DMA (CLK_DISPAUD_BASE + 10)
+#define GATE_DPU_QCH_S_DECON (CLK_DISPAUD_BASE + 11)
+#define GATE_SMMU_ABOX_QCH (CLK_DISPAUD_BASE + 12)
+#define GATE_SMMU_DPU_QCH (CLK_DISPAUD_BASE + 13)
+#define GATE_WDT_AUD_QCH (CLK_DISPAUD_BASE + 14)
+#define DOUT_CLK_AUD_ACLK (CLK_DISPAUD_BASE + 15)
+#define DOUT_CLK_AUD_AUDIF (CLK_DISPAUD_BASE + 16)
+#define DOUT_CLK_AUD_DSIF (CLK_DISPAUD_BASE + 17)
+#define DOUT_CLK_AUD_UAIF0 (CLK_DISPAUD_BASE + 18)
+#define DOUT_CLK_AUD_UAIF1 (CLK_DISPAUD_BASE + 19)
+#define DOUT_CLK_AUD_UAIF2 (CLK_DISPAUD_BASE + 20)
+#define PLL_OUT_AUD (CLK_DISPAUD_BASE + 21)
+
+/* NUMBER FOR FSYS DRIVER STARTS FROM 300 */
+#define CLK_FSYS_BASE (300)
+#define UMUX_CLKCMU_FSYS_BUS (CLK_FSYS_BASE + 0)
+#define UMUX_CLKCMU_FSYS_MMC_EMBD (CLK_FSYS_BASE + 1)
+#define UMUX_CLKCMU_FSYS_MMC_CARD (CLK_FSYS_BASE + 2)
+#define UMUX_CLKCMU_FSYS_UFS_EMBD (CLK_FSYS_BASE + 3)
+#define GATE_MMC_CARD_QCH (CLK_FSYS_BASE + 4)
+#define GATE_MMC_EMBD_QCH (CLK_FSYS_BASE + 5)
+#define GATE_RTIC_QCH (CLK_FSYS_BASE + 6)
+#define GATE_SSS_QCH (CLK_FSYS_BASE + 7)
+#define GATE_UFS_EMBD_QCH_UFS (CLK_FSYS_BASE + 8)
+#define GATE_UFS_EMBD_QCH_FMP (CLK_FSYS_BASE + 9)
+#define MMC_EMBD (CLK_FSYS_BASE + 10)
+#define MMC_CARD (CLK_FSYS_BASE + 11)
+#define UFS_EMBD (CLK_FSYS_BASE + 12)
+
+/* NUMBER FOR G2D DRIVER STARTS FROM 350 */
+#define CLK_G2D_BASE (350)
+#define UMUX_CLKCMU_G2D_G2D (CLK_G2D_BASE + 0)
+#define UMUX_CLKCMU_G2D_MSCL (CLK_G2D_BASE + 1)
+#define GATE_G2D_QCH (CLK_G2D_BASE + 2)
+#define GATE_JPEG_QCH (CLK_G2D_BASE + 3)
+#define GATE_MSCL_QCH (CLK_G2D_BASE + 4)
+#define GATE_SYSMMU_G2D_QCH (CLK_G2D_BASE + 5)
+
+/* NUMBER FOR G3D DRIVER STARTS FROM 400 */
+#define CLK_G3D_BASE (400)
+#define GATE_G3D_QCH (CLK_G3D_BASE + 0)
+
+/* NUMBER FOR ISP DRIVER STARTS FROM 450 */
+#define CLK_ISP_BASE (450)
+#define UMUX_CLKCMU_ISP_BUS (CLK_ISP_BASE + 0)
+#define UMUX_CLKCMU_ISP_GDC (CLK_ISP_BASE + 1)
+#define UMUX_CLKCMU_ISP_VRA (CLK_ISP_BASE + 2)
+#define GATE_IS6P10P0_ISP_QCH_S_ISP_ISP (CLK_ISP_BASE + 3)
+#define GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC (CLK_ISP_BASE + 4)
+#define GATE_IS6P10P0_ISP_QCH_S_ISP_VRA (CLK_ISP_BASE + 5)
+#define GATE_IS6P10P0_ISP_QCH_S_ISP_GDC (CLK_ISP_BASE + 6)
+#define GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0 (CLK_ISP_BASE + 7)
+#define GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1 (CLK_ISP_BASE + 8)
+
+/* NUMBER FOR MFC DRIVER STARTS FROM 500 */
+#define CLK_MFC_BASE (500)
+#define UMUX_CLKCMU_MFC_MFC (CLK_MFC_BASE + 0)
+#define UMUX_CLKCMU_MFC_WFD (CLK_MFC_BASE + 1)
+#define GATE_MFC_QCH (CLK_MFC_BASE + 2)
+#define GATE_SYSMMU_MFCD0_QCH (CLK_MFC_BASE + 3)
+#define GATE_SYSMMU_MFCD1_QCH (CLK_MFC_BASE + 4)
+#define GATE_WFD_QCH (CLK_MFC_BASE + 5)
+
+/* NUMBER FOR PERI DRIVER STARTS FROM 550 */
+#define CLK_PERI_BASE (550)
+#define UMUX_CLKCMU_PERI_UART (CLK_PERI_BASE + 0)
+#define GATE_CAMI2C_0_QCH (CLK_PERI_BASE + 1)
+#define GATE_CAMI2C_1_QCH (CLK_PERI_BASE + 2)
+#define GATE_CAMI2C_2_QCH (CLK_PERI_BASE + 3)
+#define GATE_CAMI2C_3_QCH (CLK_PERI_BASE + 4)
+#define GATE_I2C_0_QCH (CLK_PERI_BASE + 5)
+#define GATE_I2C_1_QCH (CLK_PERI_BASE + 6)
+#define GATE_I2C_2_QCH (CLK_PERI_BASE + 7)
+#define GATE_I2C_3_QCH (CLK_PERI_BASE + 8)
+#define GATE_I2C_4_QCH (CLK_PERI_BASE + 9)
+#define GATE_I2C_5_QCH (CLK_PERI_BASE + 10)
+#define GATE_I2C_6_QCH (CLK_PERI_BASE + 11)
+#define GATE_MCT_QCH (CLK_PERI_BASE + 12)
+#define GATE_OTP_CON_TOP_QCH (CLK_PERI_BASE + 13)
+#define GATE_PWM_MOTOR_QCH (CLK_PERI_BASE + 14)
+#define GATE_SPI_0_QCH (CLK_PERI_BASE + 15)
+#define GATE_SPI_1_QCH (CLK_PERI_BASE + 16)
+#define GATE_SPI_2_QCH (CLK_PERI_BASE + 17)
+#define GATE_UART_QCH (CLK_PERI_BASE + 18)
+#define GATE_USI00_I2C_QCH (CLK_PERI_BASE + 19)
+#define GATE_USI00_USI_QCH (CLK_PERI_BASE + 20)
+#define GATE_WDT_CLUSTER0_QCH (CLK_PERI_BASE + 21)
+#define GATE_WDT_CLUSTER1_QCH (CLK_PERI_BASE + 22)
+#define UART (CLK_PERI_BASE + 23)
+#define I2C (CLK_PERI_BASE + 24)
+#define SPI0 (CLK_PERI_BASE + 25)
+#define SPI1 (CLK_PERI_BASE + 26)
+#define SPI2 (CLK_PERI_BASE + 27)
+#define USI_I2C (CLK_PERI_BASE + 28)
+#define USI_USI (CLK_PERI_BASE + 29)
+
+/* NUMBER FOR SHUB DRIVER STARTS FROM 600 */
+#define CLK_SHUB_BASE (600)
+#define UMUX_CLKCMU_SHUB_BUS (CLK_SHUB_BASE + 0)
+#define MUX_SHUB_I2C (CLK_SHUB_BASE + 1)
+#define MUX_SHUB_USI00 (CLK_SHUB_BASE + 2)
+#define MUX_SHUB_USI01 (CLK_SHUB_BASE + 3)
+#define GATE_CM4_SHUB_QCH (CLK_SHUB_BASE + 4)
+#define GATE_I2C_SHUB00_QCH (CLK_SHUB_BASE + 5)
+#define GATE_PDMA_SHUB_QCH (CLK_SHUB_BASE + 6)
+#define GATE_PWM_SHUB_QCH (CLK_SHUB_BASE + 7)
+#define GATE_TIMER_SHUB_QCH (CLK_SHUB_BASE + 8)
+#define GATE_USI_SHUB00_QCH (CLK_SHUB_BASE + 9)
+#define GATE_WDT_SHUB_QCH (CLK_SHUB_BASE + 10)
+
+/* NUMBER FOR USB DRIVER STARTS FROM 650 */
+#define CLK_USB_BASE (650)
+#define UMUX_CLKCMU_USB_USBDRD30 (CLK_USB_BASE + 0)
+#define UMUX_CLKCMU_USB_DPGTC (CLK_USB_BASE + 1)
+#define GATE_DP_LINK_QCH_DP (CLK_USB_BASE + 2)
+#define GATE_DP_LINK_QCH_GTC (CLK_USB_BASE + 3)
+#define GATE_USB30DRD_QCH_USB30 (CLK_USB_BASE + 4)
+#define GATE_USB30DRD_QCH_USBPHY_30CTRL_0 (CLK_USB_BASE + 5)
+#define GATE_USB30DRD_QCH_USBPHY_30CTRL_1 (CLK_USB_BASE + 6)
+#define GATE_USB30DRD_QCH_USBPHY_20CTRL (CLK_USB_BASE + 7)
+#define USB30DRD (CLK_USB_BASE + 8)
+#define DP_LINK (CLK_USB_BASE + 9)
+
+/* NUMBER FOR VIPX1 DRIVER STARTS FROM 700 */
+#define CLK_VIPX1_BASE (700)
+#define UMUX_CLKCMU_VIPX1_BUS (CLK_VIPX1_BASE + 0)
+#define GATE_SMMU_D_VIPX1_QCH (CLK_VIPX1_BASE + 1)
+#define GATE_VIPX1_QCH (CLK_VIPX1_BASE + 2)
+
+/* NUMBER FOR VIPX2 DRIVER STARTS FROM 750 */
+#define CLK_VIPX2_BASE (750)
+#define UMUX_CLKCMU_VIPX2_BUS (CLK_VIPX2_BASE + 0)
+#define GATE_SMMU_D_VIPX2_QCH (CLK_VIPX2_BASE + 1)
+#define GATE_VIPX2_QCH (CLK_VIPX2_BASE + 2)
+#define GATE_VIPX2_QCH_LOCAL (CLK_VIPX2_BASE + 3)
+
+/* NUMBER FOR CLKOUT DRIVER STARTS FROM 800 */
+#define CLK_CLKOUT_BASE (800)
+#define OSC_NFC (CLK_CLKOUT_BASE + 0)
+#define OSC_AUD (CLK_CLKOUT_BASE + 1)
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS (820 + 1)
+
+#define ACPM_DVFS_MIF (0x0B040000)
+#define ACPM_DVFS_INT (0x0B040001)
+#define ACPM_DVFS_CPUCL0 (0x0B040002)
+#define ACPM_DVFS_CPUCL1 (0x0B040003)
+#define ACPM_DVFS_G3D (0x0B040004)
+#define ACPM_DVFS_INTCAM (0x0B040005)
+#define ACPM_DVFS_CAM (0x0B040006)
+#define ACPM_DVFS_DISP (0x0B040007)
+#define ACPM_DVFS_AUD (0x0B040008)
+#define ACPM_DVFS_CP (0x0B040009)
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_9610_H */
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff