incdir-y := $(notdir $(machdir-y))
-incdir-$(CONFIG_SH_SOLUTION_ENGINE) := se
incdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) := se7751
-incdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se7300
-incdir-$(CONFIG_SH_73180_SOLUTION_ENGINE) := se73180
incdir-$(CONFIG_SH_HP6XX) := hp6xx
ifneq ($(machdir-y),)
#include <linux/pci.h>
#include "../../../drivers/pci/pci-sh7751.h"
-extern void *area5_io8_base; /* Area 5 8bit I/O Base address */
extern void *area6_io8_base; /* Area 6 8bit I/O Base address */
extern void *area5_io16_base; /* Area 5 16bit I/O Base address */
-extern void *area6_io16_base; /* Area 6 16bit I/O Base address */
/*
* The 7751R HS7751RVoIP uses the built-in PCI controller (PCIC)
#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR)
#define PCI_IO_AREA SH7751_PCI_IO_BASE
#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE
-
#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK))
-#if defined(CONFIG_HS7751RVOIP_CODEC)
#define CODEC_IO_BASE 0x1000
-#endif
-
-#define maybebadio(name,port) \
- printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \
- #name, (port), (__u32) __builtin_return_address(0))
+#define CODEC_IOMAP(a) ((unsigned long)area6_io8_base + ((a) - CODEC_IO_BASE))
static inline void delay(void)
{
else
return ((unsigned long)area5_io16_base + 0x800 + ((port-0x1f0) << 1));
else
- maybebadio(port2adr, (unsigned long)port);
+ maybebadio((unsigned long)port);
return port;
}
unsigned char hs7751rvoip_inb(unsigned long port)
{
if (PXSEG(port))
- return *(volatile unsigned char *)port;
+ return ctrl_inb(port);
#if defined(CONFIG_HS7751RVOIP_CODEC)
else if (codec_port(port))
- return *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE));
+ return ctrl_inb(CODEC_IOMAP(port));
#endif
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- return *(volatile unsigned char *)PCI_IOMAP(port);
+ return ctrl_inb(PCI_IOMAP(port));
else
- return (*(volatile unsigned short *)port2adr(port) & 0xff);
+ return ctrl_inw(port2adr(port)) & 0xff;
}
unsigned char hs7751rvoip_inb_p(unsigned long port)
unsigned char v;
if (PXSEG(port))
- v = *(volatile unsigned char *)port;
+ v = ctrl_inb(port);
#if defined(CONFIG_HS7751RVOIP_CODEC)
else if (codec_port(port))
- v = *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE));
+ v = ctrl_inb(CODEC_IOMAP(port));
#endif
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- v = *(volatile unsigned char *)PCI_IOMAP(port);
+ v = ctrl_inb(PCI_IOMAP(port));
else
- v = (*(volatile unsigned short *)port2adr(port) & 0xff);
+ v = ctrl_inw(port2adr(port)) & 0xff;
delay();
return v;
}
unsigned short hs7751rvoip_inw(unsigned long port)
{
if (PXSEG(port))
- return *(volatile unsigned short *)port;
+ return ctrl_inw(port);
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- return *(volatile unsigned short *)PCI_IOMAP(port);
+ return ctrl_inw(PCI_IOMAP(port));
else
- maybebadio(inw, port);
+ maybebadio(port);
return 0;
}
unsigned int hs7751rvoip_inl(unsigned long port)
{
if (PXSEG(port))
- return *(volatile unsigned long *)port;
+ return ctrl_inl(port);
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- return *(volatile unsigned long *)PCI_IOMAP(port);
+ return ctrl_inl(PCI_IOMAP(port));
else
- maybebadio(inl, port);
+ maybebadio(port);
return 0;
}
{
if (PXSEG(port))
- *(volatile unsigned char *)port = value;
+ ctrl_outb(value, port);
#if defined(CONFIG_HS7751RVOIP_CODEC)
else if (codec_port(port))
- *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)) = value;
+ ctrl_outb(value, CODEC_IOMAP(port));
#endif
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- *(unsigned char *)PCI_IOMAP(port) = value;
+ ctrl_outb(value, PCI_IOMAP(port));
else
- *(volatile unsigned short *)port2adr(port) = value;
+ ctrl_outb(value, port2adr(port));
}
void hs7751rvoip_outb_p(unsigned char value, unsigned long port)
{
if (PXSEG(port))
- *(volatile unsigned char *)port = value;
+ ctrl_outb(value, port);
#if defined(CONFIG_HS7751RVOIP_CODEC)
else if (codec_port(port))
- *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)) = value;
+ ctrl_outb(value, CODEC_IOMAP(port));
#endif
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- *(unsigned char *)PCI_IOMAP(port) = value;
+ ctrl_outb(value, PCI_IOMAP(port));
else
- *(volatile unsigned short *)port2adr(port) = value;
+ ctrl_outw(value, port2adr(port));
+
delay();
}
void hs7751rvoip_outw(unsigned short value, unsigned long port)
{
if (PXSEG(port))
- *(volatile unsigned short *)port = value;
+ ctrl_outw(value, port);
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- *(unsigned short *)PCI_IOMAP(port) = value;
+ ctrl_outw(value, PCI_IOMAP(port));
else
- maybebadio(outw, port);
+ maybebadio(port);
}
void hs7751rvoip_outl(unsigned int value, unsigned long port)
{
if (PXSEG(port))
- *(volatile unsigned long *)port = value;
+ ctrl_outl(value, port);
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- *((unsigned long *)PCI_IOMAP(port)) = value;
+ ctrl_outl(value, PCI_IOMAP(port));
else
- maybebadio(outl, port);
+ maybebadio(port);
}
void hs7751rvoip_insb(unsigned long port, void *addr, unsigned long count)
{
+ u8 *buf = addr;
+
if (PXSEG(port))
- while (count--) *((unsigned char *) addr)++ = *(volatile unsigned char *)port;
+ while (count--)
+ *buf++ = ctrl_inb(port);
#if defined(CONFIG_HS7751RVOIP_CODEC)
else if (codec_port(port))
- while (count--) *((unsigned char *) addr)++ = *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE));
+ while (count--)
+ *buf++ = ctrl_inb(CODEC_IOMAP(port));
#endif
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) {
- volatile __u8 *bp = (__u8 *)PCI_IOMAP(port);
+ volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
- while (count--) *((volatile unsigned char *) addr)++ = *bp;
+ while (count--)
+ *buf++ = *bp;
} else {
- volatile __u16 *p = (volatile unsigned short *)port2adr(port);
+ volatile u16 *p = (volatile u16 *)port2adr(port);
- while (count--) *((unsigned char *) addr)++ = *p & 0xff;
+ while (count--)
+ *buf++ = *p & 0xff;
}
}
void hs7751rvoip_insw(unsigned long port, void *addr, unsigned long count)
{
- volatile __u16 *p;
+ volatile u16 *p;
+ u16 *buf = addr;
if (PXSEG(port))
- p = (volatile unsigned short *)port;
+ p = (volatile u16 *)port;
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- p = (volatile unsigned short *)PCI_IOMAP(port);
+ p = (volatile u16 *)PCI_IOMAP(port);
else
- p = (volatile unsigned short *)port2adr(port);
- while (count--) *((__u16 *) addr)++ = *p;
+ p = (volatile u16 *)port2adr(port);
+ while (count--)
+ *buf++ = *p;
}
void hs7751rvoip_insl(unsigned long port, void *addr, unsigned long count)
{
+
if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) {
- volatile __u32 *p = (__u32 *)PCI_IOMAP(port);
+ volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
+ u32 *buf = addr;
- while (count--) *((__u32 *) addr)++ = *p;
+ while (count--)
+ *buf++ = *p;
} else
- maybebadio(insl, port);
+ maybebadio(port);
}
void hs7751rvoip_outsb(unsigned long port, const void *addr, unsigned long count)
{
+ const u8 *buf = addr;
+
if (PXSEG(port))
- while (count--) *(volatile unsigned char *)port = *((unsigned char *) addr)++;
+ while (count--)
+ ctrl_outb(*buf++, port);
#if defined(CONFIG_HS7751RVOIP_CODEC)
else if (codec_port(port))
- while (count--) *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)) = *((unsigned char *) addr)++;
+ while (count--)
+ ctrl_outb(*buf++, CODEC_IOMAP(port));
#endif
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) {
- volatile __u8 *bp = (__u8 *)PCI_IOMAP(port);
+ volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
- while (count--) *bp = *((volatile unsigned char *) addr)++;
+ while (count--)
+ *bp = *buf++;
} else {
- volatile __u16 *p = (volatile unsigned short *)port2adr(port);
+ volatile u16 *p = (volatile u16 *)port2adr(port);
- while (count--) *p = *((unsigned char *) addr)++;
+ while (count--)
+ *p = *buf++;
}
}
void hs7751rvoip_outsw(unsigned long port, const void *addr, unsigned long count)
{
- volatile __u16 *p;
+ volatile u16 *p;
+ const u16 *buf = addr;
if (PXSEG(port))
- p = (volatile unsigned short *)port;
+ p = (volatile u16 *)port;
else if (CHECK_SH7751_PCIIO(port) || shifted_port(port))
- p = (volatile unsigned short *)PCI_IOMAP(port);
+ p = (volatile u16 *)PCI_IOMAP(port);
else
- p = (volatile unsigned short *)port2adr(port);
- while (count--) *p = *((__u16 *) addr)++;
+ p = (volatile u16 *)port2adr(port);
+
+ while (count--)
+ *p = *buf++;
}
void hs7751rvoip_outsl(unsigned long port, const void *addr, unsigned long count)
{
+ const u32 *buf = addr;
+
if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) {
- volatile __u32 *p = (__u32 *)PCI_IOMAP(port);
+ volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
- while (count--) *p = *((__u32 *) addr)++;
+ while (count--)
+ *p = *buf++;
} else
- maybebadio(outsl, port);
+ maybebadio(port);
}
-unsigned long hs7751rvoip_isa_port2addr(unsigned long offset)
+void __iomem *hs7751rvoip_ioport_map(unsigned long port, unsigned int size)
{
- return port2adr(offset);
+ if (PXSEG(port))
+ return (void __iomem *)port;
+ else if (unlikely(codec_port(port) && (size == 1)))
+ return (void __iomem *)CODEC_IOMAP(port);
+ else if (CHECK_SH7751_PCIIO(port))
+ return (void __iomem *)PCI_IOMAP(port);
+
+ return (void __iomem *)port2adr(port);
}
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/pm.h>
-#include <asm/hs7751rvoip/hs7751rvoip.h>
-#include <asm/hs7751rvoip/io.h>
#include <asm/io.h>
+#include <asm/hs7751rvoip/hs7751rvoip.h>
#include <asm/machvec.h>
#include <asm/rtc.h>
#include <asm/irq.h>
.mv_outsw = hs7751rvoip_outsw,
.mv_outsl = hs7751rvoip_outsl,
- .mv_isa_port2addr = hs7751rvoip_isa_port2addr,
.mv_init_irq = hs7751rvoip_init_irq,
+ .mv_ioport_map = hs7751rvoip_ioport_map,
};
ALIAS_MV(hs7751rvoip)
#include <linux/kernel.h>
#include <linux/types.h>
-#include <asm/systemh/7751systemh.h>
+#include <linux/pci.h>
+#include <asm/systemh7751.h>
#include <asm/addrspace.h>
#include <asm/io.h>
-
-#include <linux/pci.h>
#include "../../../drivers/pci/pci-sh7751.h"
/*
#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK))
#define ETHER_IOMAP(adr) (0xB3000000 + (adr)) /*map to 16bits access area
of smc lan chip*/
-
-#define maybebadio(name,port) \
- printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \
- #name, (port), (__u32) __builtin_return_address(0))
-
static inline void delay(void)
{
ctrl_inw(0xa0000000);
{
if (port >= 0x2000)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-#if 0
- else
- return (volatile __u16 *) (PA_SUPERIO + (port << 1));
-#endif
- maybebadio(name,(unsigned long)port);
+ maybebadio((unsigned long)port);
return (volatile __u16*)port;
}
else if (port <= 0x3F1)
return *(volatile unsigned int *)ETHER_IOMAP(port);
else
- maybebadio(inw, port);
+ maybebadio(port);
return 0;
}
else if (port <= 0x3F1)
return *(volatile unsigned int *)ETHER_IOMAP(port);
else
- maybebadio(inl, port);
+ maybebadio(port);
return 0;
}
else if (port <= 0x3F1)
*(volatile unsigned short *)ETHER_IOMAP(port) = value;
else
- maybebadio(outw, port);
+ maybebadio(port);
}
void sh7751systemh_outl(unsigned int value, unsigned long port)
else if (CHECK_SH7751_PCIIO(port))
*((unsigned long*)PCI_IOMAP(port)) = value;
else
- maybebadio(outl, port);
+ maybebadio(port);
}
void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count)
void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count)
{
- maybebadio(insl, port);
+ maybebadio(port);
}
void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count)
void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count)
{
- maybebadio(outsw, port);
-}
-
-/* For read/write calls, just copy generic (pass-thru); PCIMBR is */
-/* already set up. For a larger memory space, these would need to */
-/* reset PCIMBR as needed on a per-call basis... */
-
-unsigned char sh7751systemh_readb(unsigned long addr)
-{
- return *(volatile unsigned char*)addr;
-}
-
-unsigned short sh7751systemh_readw(unsigned long addr)
-{
- return *(volatile unsigned short*)addr;
-}
-
-unsigned int sh7751systemh_readl(unsigned long addr)
-{
- return *(volatile unsigned long*)addr;
-}
-
-void sh7751systemh_writeb(unsigned char b, unsigned long addr)
-{
- *(volatile unsigned char*)addr = b;
-}
-
-void sh7751systemh_writew(unsigned short b, unsigned long addr)
-{
- *(volatile unsigned short*)addr = b;
-}
-
-void sh7751systemh_writel(unsigned int b, unsigned long addr)
-{
- *(volatile unsigned long*)addr = b;
-}
-
-\f
-
-/* Map ISA bus address to the real address. Only for PCMCIA. */
-
-/* ISA page descriptor. */
-static __u32 sh_isa_memmap[256];
-
-#if 0
-static int
-sh_isa_mmap(__u32 start, __u32 length, __u32 offset)
-{
- int idx;
-
- if (start >= 0x100000 || (start & 0xfff) || (length != 0x1000))
- return -1;
-
- idx = start >> 12;
- sh_isa_memmap[idx] = 0xb8000000 + (offset &~ 0xfff);
- printk("sh_isa_mmap: start %x len %x offset %x (idx %x paddr %x)\n",
- start, length, offset, idx, sh_isa_memmap[idx]);
- return 0;
-}
-#endif
-
-unsigned long
-sh7751systemh_isa_port2addr(unsigned long offset)
-{
- int idx;
-
- idx = (offset >> 12) & 0xff;
- offset &= 0xfff;
- return sh_isa_memmap[idx] + offset;
+ maybebadio(port);
}
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <asm/io.h>
-#include <asm/mach/7751systemh.h>
+#include <asm/systemh7751.h>
#include <asm/smc37c93x.h>
/* address of external interrupt mask register
* for more details.
*/
#include <linux/init.h>
-#include <asm/mach/7751systemh.h>
-#include <asm/mach/io.h>
#include <asm/machvec.h>
+#include <asm/systemh7751.h>
extern void make_systemh_irq(unsigned int irq);
*/
void __init init_7751systemh_IRQ(void)
{
-/* make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); LAN */
-/* make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-4); */
make_systemh_irq(0xb); /* Ethernet interrupt */
}
.mv_outsw = sh7751systemh_outsw,
.mv_outsl = sh7751systemh_outsl,
- .mv_readb = sh7751systemh_readb,
- .mv_readw = sh7751systemh_readw,
- .mv_readl = sh7751systemh_readl,
- .mv_writeb = sh7751systemh_writeb,
- .mv_writew = sh7751systemh_writew,
- .mv_writel = sh7751systemh_writel,
-
- .mv_isa_port2addr = sh7751systemh_isa_port2addr,
-
.mv_init_irq = init_7751systemh_IRQ,
};
ALIAS_MV(7751systemh)
*/
#include <linux/kernel.h>
-#include <asm/mach/se7300.h>
#include <asm/io.h>
+#include <asm/se7300.h>
#define badio(fn, a) panic("bad i/o operation %s for %08lx.", #fn, a)
badio(inw, port);
}
+#ifdef CONFIG_SMC91X
/* MSTLANEX01 LAN at 0xb400:0000 */
static struct iop laniop = {
.start = 0x300,
.outb = simple_outb,
.outw = simple_outw,
};
+#endif
/* NE2000 pc card NIC */
static struct iop neiop = {
.outw = simple_outw,
};
+#ifdef CONFIG_IDE
/* CF in CF slot */
static struct iop cfiop = {
.base = 0xb0600000,
.outb = pcc_outb,
.outw = simple_outw,
};
+#endif
static __inline__ struct iop *
port2iop(unsigned long port)
{
if (0) ;
-#if defined(CONFIG_SMC91111)
+#if defined(CONFIG_SMC91X)
else if (laniop.check(&laniop, port))
return &laniop;
#endif
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/io.h>
-#include <asm/mach/se7300.h>
+#include <asm/se7300.h>
/*
* Initialize IRQ setting
*/
#include <linux/sched.h>
-#include <asm/mach/se7300.h>
-
-static void
-mach_led(int position, int value)
-{
- volatile unsigned short *p = (volatile unsigned short *) PA_LED;
-
- if (value) {
- *p |= (1 << 8);
- } else {
- *p &= ~(1 << 8);
- }
-}
-
+#include <asm/se7300.h>
/* Cycle the LED's in the clasic Knightrider/Sun pattern */
-void
-heartbeat_7300se(void)
+void heartbeat_7300se(void)
{
static unsigned int cnt = 0, period = 0;
volatile unsigned short *p = (volatile unsigned short *) PA_LED;
#include <linux/init.h>
#include <asm/machvec.h>
-#include <asm/machvec_init.h>
-#include <asm/mach/io.h>
+#include <asm/se7300.h>
void heartbeat_7300se(void);
void init_7300se_IRQ(void);
#include <linux/init.h>
#include <asm/machvec.h>
-#include <asm/machvec_init.h>
-#include <asm/mach/io.h>
+#include <asm/se73180.h>
void heartbeat_73180se(void);
void init_73180se_IRQ(void);
-/* $Id: io.c,v 1.5 2004/02/22 23:08:43 kkojima Exp $
+/* $Id: io.c,v 1.6 2006/01/04 17:53:54 lethal Exp $
*
* linux/arch/sh/kernel/io_se.c
*
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/io.h>
-#include <asm/se/se.h>
+#include <asm/se.h>
/* SH pcmcia io window base, start and end. */
int sh_pcic_io_wbase = 0xb8400000;
return 1;
}
-#define maybebadio(name,port) \
- printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \
- #name, (port), (__u32) __builtin_return_address(0))
-
unsigned char se_inb(unsigned long port)
{
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
(sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
return *port2adr(port);
else
- maybebadio(inw, port);
+ maybebadio(port);
return 0;
}
unsigned int se_inl(unsigned long port)
{
- maybebadio(inl, port);
+ maybebadio(port);
return 0;
}
(sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
*port2adr(port) = value;
else
- maybebadio(outw, port);
+ maybebadio(port);
}
void se_outl(unsigned int value, unsigned long port)
{
- maybebadio(outl, port);
+ maybebadio(port);
}
void se_insb(unsigned long port, void *addr, unsigned long count)
void se_insl(unsigned long port, void *addr, unsigned long count)
{
- maybebadio(insl, port);
+ maybebadio(port);
}
void se_outsb(unsigned long port, const void *addr, unsigned long count)
void se_outsl(unsigned long port, const void *addr, unsigned long count)
{
- maybebadio(outsw, port);
-}
-
-/* Map ISA bus address to the real address. Only for PCMCIA. */
-
-/* ISA page descriptor. */
-static __u32 sh_isa_memmap[256];
-
-static int
-sh_isa_mmap(__u32 start, __u32 length, __u32 offset)
-{
- int idx;
-
- if (start >= 0x100000 || (start & 0xfff) || (length != 0x1000))
- return -1;
-
- idx = start >> 12;
- sh_isa_memmap[idx] = 0xb8000000 + (offset &~ 0xfff);
-#if 0
- printk("sh_isa_mmap: start %x len %x offset %x (idx %x paddr %x)\n",
- start, length, offset, idx, sh_isa_memmap[idx]);
-#endif
- return 0;
-}
-
-unsigned long
-se_isa_port2addr(unsigned long offset)
-{
- int idx;
-
- idx = (offset >> 12) & 0xff;
- offset &= 0xfff;
- return sh_isa_memmap[idx] + offset;
+ maybebadio(port);
}
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/io.h>
-#include <asm/se/se.h>
+#include <asm/se.h>
/*
* Initialize IRQ setting
*/
#include <linux/sched.h>
-#include <asm/se/se.h>
+#include <asm/se.h>
/* Cycle the LED's in the clasic Knightrider/Sun pattern */
void heartbeat_se(void)
#include <asm/machvec.h>
#include <asm/rtc.h>
-#include <asm/machvec_init.h>
-
-#include <asm/se/io.h>
+#include <asm/se.h>
void heartbeat_se(void);
-void setup_se(void);
void init_se_IRQ(void);
/*
.mv_outsw = se_outsw,
.mv_outsl = se_outsl,
- .mv_isa_port2addr = se_isa_port2addr,
-
.mv_init_irq = init_se_IRQ,
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = heartbeat_se,
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <asm/io.h>
-#include <asm/se/se.h>
+#include <asm/se.h>
#include <asm/smc37c93x.h>
/*
-/*
+/*
* linux/arch/sh/kernel/io_7751se.c
*
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/io.h>
-#include <asm/se7751/se7751.h>
+#include <asm/se7751.h>
#include <asm/addrspace.h>
#include <linux/pci.h>
#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK))
-#define maybebadio(name,port) \
- printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \
- #name, (port), (__u32) __builtin_return_address(0))
-
static inline void delay(void)
{
ctrl_inw(0xa0000000);
{
if (port >= 0x2000)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-#if 0
- else
- return (volatile __u16 *) (PA_SUPERIO + (port << 1));
-#endif
- maybebadio(name,(unsigned long)port);
+ maybebadio((unsigned long)port);
return (volatile __u16*)port;
}
else if (port >= 0x2000)
return *port2adr(port);
else
- maybebadio(inw, port);
+ maybebadio(port);
return 0;
}
else if (port >= 0x2000)
return *port2adr(port);
else
- maybebadio(inl, port);
+ maybebadio(port);
return 0;
}
else if (port >= 0x2000)
*port2adr(port) = value;
else
- maybebadio(outw, port);
+ maybebadio(port);
}
void sh7751se_outl(unsigned int value, unsigned long port)
else if (CHECK_SH7751_PCIIO(port))
*((unsigned long*)PCI_IOMAP(port)) = value;
else
- maybebadio(outl, port);
+ maybebadio(port);
}
void sh7751se_insl(unsigned long port, void *addr, unsigned long count)
{
- maybebadio(insl, port);
+ maybebadio(port);
}
void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count)
{
- maybebadio(outsw, port);
+ maybebadio(port);
}
/* Map ISA bus address to the real address. Only for PCMCIA. */
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/irq.h>
-#include <asm/se7751/se7751.h>
+#include <asm/se7751.h>
/*
* Initialize IRQ setting
*
* This file contains Solution Engine specific LED code.
*/
-
-#include <asm/se7751/se7751.h>
#include <linux/sched.h>
+#include <asm/se7751.h>
/* Cycle the LED's in the clasic Knightrider/Sun pattern */
void heartbeat_7751se(void)
*/
#include <linux/init.h>
-
#include <asm/machvec.h>
-#include <asm/rtc.h>
-#include <asm/machvec_init.h>
-
-#include <asm/se7751/io.h>
+#include <asm/se7751.h>
void heartbeat_7751se(void);
void init_7751se_IRQ(void);
.mv_insl = sh7751se_insl,
.mv_outsl = sh7751se_outsl,
- .mv_isa_port2addr = sh7751se_isa_port2addr,
-
.mv_init_irq = init_7751se_IRQ,
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = heartbeat_7751se,
-/*
+/*
* linux/arch/sh/kernel/setup_7751se.c
*
* Copyright (C) 2000 Kazumoto Kojima
#include <linux/init.h>
#include <linux/irq.h>
-
-#include <linux/hdreg.h>
#include <linux/ide.h>
#include <asm/io.h>
-#include <asm/se7751/se7751.h>
+#include <asm/se7751.h>
#ifdef CONFIG_SH_KGDB
#include <asm/kgdb.h>
#include <linux/init.h>
#include <linux/irq.h>
-#include <linux/hdreg.h>
-#include <linux/ide.h>
#include <asm/io.h>
+#include <asm/rtc.h>
#include <asm/sh03/io.h>
#include <asm/sh03/sh03.h>
#include <asm/addrspace.h>
#include "../../drivers/pci/pci-sh7751.h"
-extern void (*board_time_init)(void);
-
const char *get_system_type(void)
{
return "Interface CTP/PCI-SH03)";
}
-void init_sh03_IRQ(void)
+static void init_sh03_IRQ(void)
{
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
extern void *cf_io_base;
-unsigned long sh03_isa_port2addr(unsigned long port)
+static void __iomem *sh03_ioport_map(unsigned long port, unsigned int size)
{
if (PXSEG(port))
- return port;
+ return (void __iomem *)port;
/* CompactFlash (IDE) */
- if (((port >= 0x1f0) && (port <= 0x1f7)) || (port == 0x3f6)) {
- return (unsigned long)cf_io_base + port;
- }
- return port + SH7751_PCI_IO_BASE;
-}
+ if (((port >= 0x1f0) && (port <= 0x1f7)) || (port == 0x3f6))
+ return (void __iomem *)((unsigned long)cf_io_base + port);
-/*
- * The Machine Vector
- */
+ return (void __iomem *)(port + SH7751_PCI_IO_BASE);
+}
struct sh_machine_vector mv_sh03 __initmv = {
.mv_nr_irqs = 48,
- .mv_isa_port2addr = sh03_isa_port2addr,
+ .mv_ioport_map = sh03_ioport_map,
.mv_init_irq = init_sh03_IRQ,
#ifdef CONFIG_HEARTBEAT
/*
* The SnapGear uses the built-in PCI controller (PCIC)
* of the 7751 processor
- */
+ */
#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR)
#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR)
#define PCI_IO_AREA SH7751_PCI_IO_BASE
#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE
-
#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK))
-
-#define maybebadio(name,port) \
- printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \
- #name, (port), (__u32) __builtin_return_address(0))
-
-
static inline void delay(void)
{
ctrl_inw(0xa0000000);
}
-
static inline volatile __u16 *port2adr(unsigned int port)
{
-#if 0
- if (port >= 0x2000)
- return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-#endif
- maybebadio(name,(unsigned long)port);
+ maybebadio((unsigned long)port);
return (volatile __u16*)port;
}
-
/* In case someone configures the kernel w/o PCI support: in that */
/* scenario, don't ever bother to check for PCI-window addresses */
else if (port >= 0x2000)
return *port2adr(port);
else
- maybebadio(inw, port);
+ maybebadio(port);
return 0;
}
else if (port >= 0x2000)
return *port2adr(port);
else
- maybebadio(inl, port);
+ maybebadio(port);
return 0;
}
else if (port >= 0x2000)
*port2adr(port) = value;
else
- maybebadio(outw, port);
+ maybebadio(port);
}
else if (CHECK_SH7751_PCIIO(port))
*((unsigned long*)PCI_IOMAP(port)) = value;
else
- maybebadio(outl, port);
+ maybebadio(port);
}
void snapgear_insl(unsigned long port, void *addr, unsigned long count)
{
- maybebadio(insl, port);
+ maybebadio(port);
}
void snapgear_outsl(unsigned long port, const void *addr, unsigned long count)
{
- maybebadio(outsw, port);
-}
-
-/* Map ISA bus address to the real address. Only for PCMCIA. */
-
-
-/* ISA page descriptor. */
-static __u32 sh_isa_memmap[256];
-
-
-#if 0
-static int sh_isa_mmap(__u32 start, __u32 length, __u32 offset)
-{
- int idx;
-
- if (start >= 0x100000 || (start & 0xfff) || (length != 0x1000))
- return -1;
-
- idx = start >> 12;
- sh_isa_memmap[idx] = 0xb8000000 + (offset &~ 0xfff);
-#if 0
- printk("sh_isa_mmap: start %x len %x offset %x (idx %x paddr %x)\n",
- start, length, offset, idx, sh_isa_memmap[idx]);
-#endif
- return 0;
-}
-#endif
-
-unsigned long snapgear_isa_port2addr(unsigned long offset)
-{
- int idx;
-
- idx = (offset >> 12) & 0xff;
- offset &= 0xfff;
- return sh_isa_memmap[idx] + offset;
+ maybebadio(port);
}
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/mc146818rtc.h>
-
#include <asm/io.h>
-#include <asm/rtc.h>
-#include <asm/mc146818rtc.h>
/****************************************************************************/
-/****************************************************************************/
-/*
+/*
* linux/arch/sh/boards/snapgear/setup.c
*
* Copyright (C) 2002 David McCullough <davidm@snapgear.com>
* Modified for 7751 Solution Engine by
* Ian da Silva and Jeremy Siegel, 2001.
*/
-/****************************************************************************/
-
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/sched.h>
-
#include <asm/machvec.h>
-#include <asm/mach/io.h>
+#include <asm/snapgear.h>
#include <asm/irq.h>
#include <asm/io.h>
+#include <asm/rtc.h>
#include <asm/cpu/timer.h>
-extern void (*board_time_init)(void);
extern void secureedge5410_rtc_init(void);
extern void pcibios_init(void);
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
}
-/****************************************************************************/
-/*
- * Fast poll interrupt simulator.
- */
-
-/*
- * Leave all of the fast timer/fast poll stuff commented out for now, since
- * it's not clear whether it actually works or not. Since it wasn't being used
- * at all in 2.4, we'll assume it's not sane for 2.6 either.. -- PFM
- */
-#if 0
-#define FAST_POLL 1000
-//#define FAST_POLL_INTR
-
-#define FASTTIMER_IRQ 17
-#define FASTTIMER_IPR_ADDR INTC_IPRA
-#define FASTTIMER_IPR_POS 2
-#define FASTTIMER_PRIORITY 3
-
-#ifdef FAST_POLL_INTR
-#define TMU1_TCR_INIT 0x0020
-#else
-#define TMU1_TCR_INIT 0
-#endif
-#define TMU_TSTR_INIT 1
-#define TMU1_TCR_CALIB 0x0000
-
-
-#ifdef FAST_POLL_INTR
-static void fast_timer_irq(int irq, void *dev_instance, struct pt_regs *regs)
-{
- unsigned long timer_status;
- timer_status = ctrl_inw(TMU1_TCR);
- timer_status &= ~0x100;
- ctrl_outw(timer_status, TMU1_TCR);
-}
-#endif
-
-/*
- * return the current ticks on the fast timer
- */
-
-unsigned long fast_timer_count(void)
-{
- return(ctrl_inl(TMU1_TCNT));
-}
-
-/*
- * setup a fast timer for profiling etc etc
- */
-
-static void setup_fast_timer()
-{
- unsigned long interval;
-
-#ifdef FAST_POLL_INTR
- interval = (current_cpu_data.module_clock/4 + FAST_POLL/2) / FAST_POLL;
-
- make_ipr_irq(FASTTIMER_IRQ, FASTTIMER_IPR_ADDR, FASTTIMER_IPR_POS,
- FASTTIMER_PRIORITY);
-
- printk("SnapGear: %dHz fast timer on IRQ %d\n",FAST_POLL,FASTTIMER_IRQ);
-
- if (request_irq(FASTTIMER_IRQ, fast_timer_irq, 0, "SnapGear fast timer",
- NULL) != 0)
- printk("%s(%d): request_irq() failed?\n", __FILE__, __LINE__);
-#else
- printk("SnapGear: fast timer running\n",FAST_POLL,FASTTIMER_IRQ);
- interval = 0xffffffff;
-#endif
-
- ctrl_outb(ctrl_inb(TMU_TSTR) & ~0x2, TMU_TSTR); /* disable timer 1 */
- ctrl_outw(TMU1_TCR_INIT, TMU1_TCR);
- ctrl_outl(interval, TMU1_TCOR);
- ctrl_outl(interval, TMU1_TCNT);
- ctrl_outb(ctrl_inb(TMU_TSTR) | 0x2, TMU_TSTR); /* enable timer 1 */
-
- printk("Timer count 1 = 0x%x\n", fast_timer_count());
- udelay(1000);
- printk("Timer count 2 = 0x%x\n", fast_timer_count());
-}
-#endif
-
-/****************************************************************************/
-
const char *get_system_type(void)
{
return "SnapGear SecureEdge5410";
.mv_outw_p = snapgear_outw,
.mv_outl_p = snapgear_outl,
- .mv_isa_port2addr = snapgear_isa_port2addr,
-
.mv_init_irq = init_snapgear_IRQ,
};
ALIAS_MV(snapgear)
ctrl_inw(0xa0000000);
}
-static inline volatile u16 *port2adr(unsigned int port)
+static inline unsigned int port2adr(unsigned int port)
{
maybebadio((unsigned long)port);
- return (volatile u16*)port;
+ return port;
}
u8 titan_inb(unsigned long port)
Do not change this unless you know what you are doing.
+config HD64461_IOBASE
+ hex "HD64461 start address"
+ depends on HD64461
+ default "0xb0000000"
+
config HD64461_ENABLER
bool "HD64461 PCMCIA enabler"
depends on HD64461
via the HD64461 companion chip.
Otherwise, say N.
-
config HD64465_IOBASE
hex "HD64465 start address"
depends on HD64465
*/
#include <linux/init.h>
-
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
#include <asm/io.h>
#include <asm/irq.h>
/* SH4 can't access PCMCIA interface through P2 area.
* we must remap it with appropreate attribute bit of the page set.
* this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */
-#include <linux/mm.h>
-#include <linux/vmalloc.h>
#if defined(CONFIG_CF_AREA6)
#define slot_no 0
}
#if defined(CONFIG_SH_SOLUTION_ENGINE)
-#include <asm/se/se.h>
+#include <asm/se.h>
/*
* SolutionEngine
#include <asm/system.h>
#include <asm/io.h>
-#include <asm/se/se.h>
+#include <asm/se.h>
#include <asm/machvec.h>
#ifdef CONFIG_SH_STANDARD_BIOS
#include <asm/sh_bios.h>
#define IRQ_RINGING 4 /* Ringing IRQ */
#define IRQ_CODEC 5 /* CODEC IRQ */
+#define __IO_PREFIX hs7751rvoip
+#include <asm/io_generic.h>
+
/* arch/sh/boards/renesas/hs7751rvoip/irq.c */
void init_hs7751rvoip_IRQ(void);
#define CMOS_WRITE(val,addr) __CMOS_WRITE(val,addr,b)
#elif defined(CONFIG_SH_SECUREEDGE5410)
-#include <asm/snapgear/io.h>
+#include <asm/snapgear.h>
#define RTC_PORT(n) SECUREEDGE_IOPORT_ADDR
#define CMOS_READ(addr) secureedge5410_cmos_read(addr)
--- /dev/null
+#ifndef __ASM_SH_HITACHI_SE_H
+#define __ASM_SH_HITACHI_SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_se.h
+ *
+ * Copyright (C) 2000 Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+ */
+
+/* Box specific addresses. */
+
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_FROM 0x01000000 /* EPROM */
+#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0x12000000
+#define PA_EXT4_SIZE 0x02000000
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
+
+#define PA_83902 0xb0000000 /* DP83902A */
+#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
+#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
+
+#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
+#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
+#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
+#define PA_LED 0xb0c00000 /* LED */
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define PA_BCR 0xb0e00000
+#else
+#define PA_BCR 0xb1400000 /* FPGA */
+#endif
+
+#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA (PA_BCR + 0)
+#define BCR_ILCRB (PA_BCR + 2)
+#define BCR_ILCRC (PA_BCR + 4)
+#define BCR_ILCRD (PA_BCR + 6)
+#define BCR_ILCRE (PA_BCR + 8)
+#define BCR_ILCRF (PA_BCR + 10)
+#define BCR_ILCRG (PA_BCR + 12)
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define IRQ_STNIC 12
+#else
+#define IRQ_STNIC 10
+#endif
+
+#define __IO_PREFIX se
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_HITACHI_SE_H */
+++ /dev/null
-/*
- * include/asm-sh/io_se.h
- *
- * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * IO functions for an Hitachi SolutionEngine
- */
-
-#ifndef _ASM_SH_IO_SE_H
-#define _ASM_SH_IO_SE_H
-
-extern unsigned char se_inb(unsigned long port);
-extern unsigned short se_inw(unsigned long port);
-extern unsigned int se_inl(unsigned long port);
-
-extern void se_outb(unsigned char value, unsigned long port);
-extern void se_outw(unsigned short value, unsigned long port);
-extern void se_outl(unsigned int value, unsigned long port);
-
-extern unsigned char se_inb_p(unsigned long port);
-extern void se_outb_p(unsigned char value, unsigned long port);
-
-extern void se_insb(unsigned long port, void *addr, unsigned long count);
-extern void se_insw(unsigned long port, void *addr, unsigned long count);
-extern void se_insl(unsigned long port, void *addr, unsigned long count);
-extern void se_outsb(unsigned long port, const void *addr, unsigned long count);
-extern void se_outsw(unsigned long port, const void *addr, unsigned long count);
-extern void se_outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern unsigned long se_isa_port2addr(unsigned long offset);
-
-#endif /* _ASM_SH_IO_SE_H */
+++ /dev/null
-#ifndef __ASM_SH_HITACHI_SE_H
-#define __ASM_SH_HITACHI_SE_H
-
-/*
- * linux/include/asm-sh/hitachi_se.h
- *
- * Copyright (C) 2000 Kazumoto Kojima
- *
- * Hitachi SolutionEngine support
- */
-
-/* Box specific addresses. */
-
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_FROM 0x01000000 /* EPROM */
-#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-
-#define PA_EXT4 0x12000000
-#define PA_EXT4_SIZE 0x02000000
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
-
-#define PA_83902 0xb0000000 /* DP83902A */
-#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
-#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
-
-#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
-#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
-#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
-#define PA_LED 0xb0c00000 /* LED */
-#if defined(CONFIG_CPU_SUBTYPE_SH7705)
-#define PA_BCR 0xb0e00000
-#else
-#define PA_BCR 0xb1400000 /* FPGA */
-#endif
-
-#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define BCR_ILCRA (PA_BCR + 0)
-#define BCR_ILCRB (PA_BCR + 2)
-#define BCR_ILCRC (PA_BCR + 4)
-#define BCR_ILCRD (PA_BCR + 6)
-#define BCR_ILCRE (PA_BCR + 8)
-#define BCR_ILCRF (PA_BCR + 10)
-#define BCR_ILCRG (PA_BCR + 12)
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7705)
-#define IRQ_STNIC 12
-#else
-#define IRQ_STNIC 10
-#endif
-
-#endif /* __ASM_SH_HITACHI_SE_H */
--- /dev/null
+#ifndef __ASM_SH_HITACHI_SE7300_H
+#define __ASM_SH_HITACHI_SE7300_H
+
+/*
+ * linux/include/asm-sh/se/se7300.h
+ *
+ * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
+ *
+ * SH-Mobile SolutionEngine 7300 support
+ */
+
+/* Box specific addresses. */
+
+/* Area 0 */
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
+#define PA_FROM 0x00400000 /* Flash ROM */
+#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
+#define PA_SRAM 0x00800000 /* SRAM */
+#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
+/* Area 1 */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+/* Area 2 */
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+/* Area 3 */
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+/* Area 4 */
+#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+#define PA_LED 0xb0800000 /* LED */
+#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
+#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */
+#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */
+#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */
+/* Area 5 */
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+/* Area 6 */
+#define PA_LCD1 0xb8000000
+#define PA_LCD2 0xb8800000
+
+#define __IO_PREFIX sh7300se
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_HITACHI_SE7300_H */
+++ /dev/null
-/*
- * include/asm-sh/se7300/io.h
- *
- * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
- * IO functions for SH-Mobile(SH7300) SolutionEngine
- */
-
-#ifndef _ASM_SH_IO_7300SE_H
-#define _ASM_SH_IO_7300SE_H
-
-extern unsigned char sh7300se_inb(unsigned long port);
-extern unsigned short sh7300se_inw(unsigned long port);
-extern unsigned int sh7300se_inl(unsigned long port);
-
-extern void sh7300se_outb(unsigned char value, unsigned long port);
-extern void sh7300se_outw(unsigned short value, unsigned long port);
-extern void sh7300se_outl(unsigned int value, unsigned long port);
-
-extern unsigned char sh7300se_inb_p(unsigned long port);
-extern void sh7300se_outb_p(unsigned char value, unsigned long port);
-
-extern void sh7300se_insb(unsigned long port, void *addr, unsigned long count);
-extern void sh7300se_insw(unsigned long port, void *addr, unsigned long count);
-extern void sh7300se_insl(unsigned long port, void *addr, unsigned long count);
-extern void sh7300se_outsb(unsigned long port, const void *addr, unsigned long count);
-extern void sh7300se_outsw(unsigned long port, const void *addr, unsigned long count);
-extern void sh7300se_outsl(unsigned long port, const void *addr, unsigned long count);
-
-#endif /* _ASM_SH_IO_7300SE_H */
+++ /dev/null
-#ifndef __ASM_SH_HITACHI_SE7300_H
-#define __ASM_SH_HITACHI_SE7300_H
-
-/*
- * linux/include/asm-sh/se/se7300.h
- *
- * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
- *
- * SH-Mobile SolutionEngine 7300 support
- */
-
-/* Box specific addresses. */
-
-/* Area 0 */
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
-#define PA_FROM 0x00400000 /* Flash ROM */
-#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
-#define PA_SRAM 0x00800000 /* SRAM */
-#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
-/* Area 1 */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-/* Area 2 */
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-/* Area 3 */
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-/* Area 4 */
-#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
-#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-#define PA_LED 0xb0800000 /* LED */
-#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
-#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */
-#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */
-#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */
-/* Area 5 */
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-/* Area 6 */
-#define PA_LCD1 0xb8000000
-#define PA_LCD2 0xb8800000
-
-#endif /* __ASM_SH_HITACHI_SE7300_H */
--- /dev/null
+#ifndef __ASM_SH_HITACHI_SE73180_H
+#define __ASM_SH_HITACHI_SE73180_H
+
+/*
+ * include/asm-sh/se/se73180.h
+ *
+ * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
+ *
+ * SH-Mobile SolutionEngine 73180 support
+ */
+
+/* Box specific addresses. */
+
+/* Area 0 */
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
+#define PA_FROM 0x00400000 /* Flash ROM */
+#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
+#define PA_SRAM 0x00800000 /* SRAM */
+#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
+/* Area 1 */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+/* Area 2 */
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+/* Area 3 */
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+/* Area 4 */
+#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+#define PA_LED 0xb0C00000 /* LED */
+#define LED_SHIFT 0
+#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
+#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */
+#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */
+#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */
+/* Area 5 */
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+/* Area 6 */
+#define PA_LCD1 0xb8000000
+#define PA_LCD2 0xb8800000
+
+#define __IO_PREFIX sh73180se
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_HITACHI_SE73180_H */
+++ /dev/null
-/*
- * include/asm-sh/se73180/io.h
- *
- * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
- * Based on include/asm-sh/se7300/io.h
- *
- * IO functions for SH-Mobile3(SH73180) SolutionEngine
- *
- */
-
-#ifndef _ASM_SH_IO_73180SE_H
-#define _ASM_SH_IO_73180SE_H
-
-extern unsigned char sh73180se_inb(unsigned long port);
-extern unsigned short sh73180se_inw(unsigned long port);
-extern unsigned int sh73180se_inl(unsigned long port);
-
-extern void sh73180se_outb(unsigned char value, unsigned long port);
-extern void sh73180se_outw(unsigned short value, unsigned long port);
-extern void sh73180se_outl(unsigned int value, unsigned long port);
-
-extern unsigned char sh73180se_inb_p(unsigned long port);
-extern void sh73180se_outb_p(unsigned char value, unsigned long port);
-
-extern void sh73180se_insb(unsigned long port, void *addr, unsigned long count);
-extern void sh73180se_insw(unsigned long port, void *addr, unsigned long count);
-extern void sh73180se_insl(unsigned long port, void *addr, unsigned long count);
-extern void sh73180se_outsb(unsigned long port, const void *addr, unsigned long count);
-extern void sh73180se_outsw(unsigned long port, const void *addr, unsigned long count);
-extern void sh73180se_outsl(unsigned long port, const void *addr, unsigned long count);
-
-#endif /* _ASM_SH_IO_73180SE_H */
+++ /dev/null
-#ifndef __ASM_SH_HITACHI_SE73180_H
-#define __ASM_SH_HITACHI_SE73180_H
-
-/*
- * include/asm-sh/se/se73180.h
- *
- * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
- *
- * SH-Mobile SolutionEngine 73180 support
- */
-
-/* Box specific addresses. */
-
-/* Area 0 */
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
-#define PA_FROM 0x00400000 /* Flash ROM */
-#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
-#define PA_SRAM 0x00800000 /* SRAM */
-#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
-/* Area 1 */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-/* Area 2 */
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-/* Area 3 */
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-/* Area 4 */
-#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
-#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-#define PA_LED 0xb0C00000 /* LED */
-#define LED_SHIFT 0
-#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
-#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */
-#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */
-#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */
-/* Area 5 */
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-/* Area 6 */
-#define PA_LCD1 0xb8000000
-#define PA_LCD2 0xb8800000
-
-#endif /* __ASM_SH_HITACHI_SE73180_H */
--- /dev/null
+#ifndef __ASM_SH_HITACHI_7751SE_H
+#define __ASM_SH_HITACHI_7751SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_7751se.h
+ *
+ * Copyright (C) 2000 Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+
+ * Modified for 7751 Solution Engine by
+ * Ian da Silva and Jeremy Siegel, 2001.
+ */
+
+/* Box specific addresses. */
+
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_FROM 0x01000000 /* EPROM */
+#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0x12000000
+#define PA_EXT4_SIZE 0x02000000
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
+#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
+#define PA_LED 0xba000000 /* LED */
+#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE (PA_MRSHPC + 4)
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA (PA_BCR + 0)
+#define BCR_ILCRB (PA_BCR + 2)
+#define BCR_ILCRC (PA_BCR + 4)
+#define BCR_ILCRD (PA_BCR + 6)
+#define BCR_ILCRE (PA_BCR + 8)
+#define BCR_ILCRF (PA_BCR + 10)
+#define BCR_ILCRG (PA_BCR + 12)
+
+#define IRQ_79C973 13
+
+#define __IO_PREFIX sh7751se
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_HITACHI_7751SE_H */
+++ /dev/null
-/*
- * include/asm-sh/io_7751se.h
- *
- * Modified version of io_se.h for the 7751se-specific functions.
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * IO functions for an Hitachi SolutionEngine
- */
-
-#ifndef _ASM_SH_IO_7751SE_H
-#define _ASM_SH_IO_7751SE_H
-
-extern unsigned char sh7751se_inb(unsigned long port);
-extern unsigned short sh7751se_inw(unsigned long port);
-extern unsigned int sh7751se_inl(unsigned long port);
-
-extern void sh7751se_outb(unsigned char value, unsigned long port);
-extern void sh7751se_outw(unsigned short value, unsigned long port);
-extern void sh7751se_outl(unsigned int value, unsigned long port);
-
-extern unsigned char sh7751se_inb_p(unsigned long port);
-extern void sh7751se_outb_p(unsigned char value, unsigned long port);
-
-extern void sh7751se_insb(unsigned long port, void *addr, unsigned long count);
-extern void sh7751se_insw(unsigned long port, void *addr, unsigned long count);
-extern void sh7751se_insl(unsigned long port, void *addr, unsigned long count);
-extern void sh7751se_outsb(unsigned long port, const void *addr, unsigned long count);
-extern void sh7751se_outsw(unsigned long port, const void *addr, unsigned long count);
-extern void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern unsigned char sh7751se_readb(unsigned long addr);
-extern unsigned short sh7751se_readw(unsigned long addr);
-extern unsigned int sh7751se_readl(unsigned long addr);
-extern void sh7751se_writeb(unsigned char b, unsigned long addr);
-extern void sh7751se_writew(unsigned short b, unsigned long addr);
-extern void sh7751se_writel(unsigned int b, unsigned long addr);
-
-extern unsigned long sh7751se_isa_port2addr(unsigned long offset);
-
-#endif /* _ASM_SH_IO_7751SE_H */
+++ /dev/null
-#ifndef __ASM_SH_HITACHI_7751SE_H
-#define __ASM_SH_HITACHI_7751SE_H
-
-/*
- * linux/include/asm-sh/hitachi_7751se.h
- *
- * Copyright (C) 2000 Kazumoto Kojima
- *
- * Hitachi SolutionEngine support
-
- * Modified for 7751 Solution Engine by
- * Ian da Silva and Jeremy Siegel, 2001.
- */
-
-/* Box specific addresses. */
-
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_FROM 0x01000000 /* EPROM */
-#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-
-#define PA_EXT4 0x12000000
-#define PA_EXT4_SIZE 0x02000000
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
-
-#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
-#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
-#define PA_LED 0xba000000 /* LED */
-#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
-
-#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
-#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_MODE (PA_MRSHPC + 4)
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define BCR_ILCRA (PA_BCR + 0)
-#define BCR_ILCRB (PA_BCR + 2)
-#define BCR_ILCRC (PA_BCR + 4)
-#define BCR_ILCRD (PA_BCR + 6)
-#define BCR_ILCRE (PA_BCR + 8)
-#define BCR_ILCRF (PA_BCR + 10)
-#define BCR_ILCRG (PA_BCR + 12)
-
-#define IRQ_79C973 13
-
-#endif /* __ASM_SH_HITACHI_7751SE_H */
#define IRL3_IPR_POS 0
#define IRL3_PRIORITY 4
-
-extern unsigned long sh03_isa_port2addr(unsigned long offset);
-
-extern void setup_sh03(void);
-extern void init_sh03_IRQ(void);
-extern void heartbeat_sh03(void);
-
-extern void sh03_rtc_gettimeofday(struct timeval *tv);
-extern int sh03_rtc_settimeofday(const struct timeval *tv);
+void heartbeat_sh03(void);
#endif /* _ASM_SH_IO_SH03_H */
--- /dev/null
+/*
+ * include/asm-sh/snapgear/io.h
+ *
+ * Modified version of io_se.h for the snapgear-specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License. See linux/COPYING for more information.
+ *
+ * IO functions for a SnapGear
+ */
+
+#ifndef _ASM_SH_IO_SNAPGEAR_H
+#define _ASM_SH_IO_SNAPGEAR_H
+
+#if defined(CONFIG_CPU_SH4)
+/*
+ * The external interrupt lines, these take up ints 0 - 15 inclusive
+ * depending on the priority for the interrupt. In fact the priority
+ * is the interrupt :-)
+ */
+
+#define IRL0_IRQ 2
+#define IRL0_IPR_ADDR INTC_IPRD
+#define IRL0_IPR_POS 3
+#define IRL0_PRIORITY 13
+
+#define IRL1_IRQ 5
+#define IRL1_IPR_ADDR INTC_IPRD
+#define IRL1_IPR_POS 2
+#define IRL1_PRIORITY 10
+
+#define IRL2_IRQ 8
+#define IRL2_IPR_ADDR INTC_IPRD
+#define IRL2_IPR_POS 1
+#define IRL2_PRIORITY 7
+
+#define IRL3_IRQ 11
+#define IRL3_IPR_ADDR INTC_IPRD
+#define IRL3_IPR_POS 0
+#define IRL3_PRIORITY 4
+#endif
+
+#define __IO_PREFIX snapgear
+#include <asm/io_generic.h>
+
+#ifdef CONFIG_SH_SECUREEDGE5410
+/*
+ * We need to remember what was written to the ioport as some bits
+ * are shared with other functions and you cannot read back what was
+ * written :-|
+ *
+ * Bit Read Write
+ * -----------------------------------------------
+ * D0 DCD on ttySC1 power
+ * D1 Reset Switch heatbeat
+ * D2 ttySC0 CTS (7100) LAN
+ * D3 - WAN
+ * D4 ttySC0 DCD (7100) CONSOLE
+ * D5 - ONLINE
+ * D6 - VPN
+ * D7 - DTR on ttySC1
+ * D8 - ttySC0 RTS (7100)
+ * D9 - ttySC0 DTR (7100)
+ * D10 - RTC SCLK
+ * D11 RTC DATA RTC DATA
+ * D12 - RTS RESET
+ */
+
+#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
+extern unsigned short secureedge5410_ioport;
+
+#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
+ (secureedge5410_ioport = \
+ ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
+#define SECUREEDGE_READ_IOPORT() \
+ ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
+#endif
+
+#endif /* _ASM_SH_IO_SNAPGEAR_H */
+++ /dev/null
-/*
- * include/asm-sh/snapgear/io.h
- *
- * Modified version of io_se.h for the snapgear-specific functions.
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * IO functions for a SnapGear
- */
-
-#ifndef _ASM_SH_IO_SNAPGEAR_H
-#define _ASM_SH_IO_SNAPGEAR_H
-
-#if defined(CONFIG_CPU_SH4)
-/*
- * The external interrupt lines, these take up ints 0 - 15 inclusive
- * depending on the priority for the interrupt. In fact the priority
- * is the interrupt :-)
- */
-
-#define IRL0_IRQ 2
-#define IRL0_IPR_ADDR INTC_IPRD
-#define IRL0_IPR_POS 3
-#define IRL0_PRIORITY 13
-
-#define IRL1_IRQ 5
-#define IRL1_IPR_ADDR INTC_IPRD
-#define IRL1_IPR_POS 2
-#define IRL1_PRIORITY 10
-
-#define IRL2_IRQ 8
-#define IRL2_IPR_ADDR INTC_IPRD
-#define IRL2_IPR_POS 1
-#define IRL2_PRIORITY 7
-
-#define IRL3_IRQ 11
-#define IRL3_IPR_ADDR INTC_IPRD
-#define IRL3_IPR_POS 0
-#define IRL3_PRIORITY 4
-#endif
-
-extern unsigned char snapgear_inb(unsigned long port);
-extern unsigned short snapgear_inw(unsigned long port);
-extern unsigned int snapgear_inl(unsigned long port);
-
-extern void snapgear_outb(unsigned char value, unsigned long port);
-extern void snapgear_outw(unsigned short value, unsigned long port);
-extern void snapgear_outl(unsigned int value, unsigned long port);
-
-extern unsigned char snapgear_inb_p(unsigned long port);
-extern void snapgear_outb_p(unsigned char value, unsigned long port);
-
-extern void snapgear_insl(unsigned long port, void *addr, unsigned long count);
-extern void snapgear_outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern unsigned long snapgear_isa_port2addr(unsigned long offset);
-
-#ifdef CONFIG_SH_SECUREEDGE5410
-/*
- * We need to remember what was written to the ioport as some bits
- * are shared with other functions and you cannot read back what was
- * written :-|
- *
- * Bit Read Write
- * -----------------------------------------------
- * D0 DCD on ttySC1 power
- * D1 Reset Switch heatbeat
- * D2 ttySC0 CTS (7100) LAN
- * D3 - WAN
- * D4 ttySC0 DCD (7100) CONSOLE
- * D5 - ONLINE
- * D6 - VPN
- * D7 - DTR on ttySC1
- * D8 - ttySC0 RTS (7100)
- * D9 - ttySC0 DTR (7100)
- * D10 - RTC SCLK
- * D11 RTC DATA RTC DATA
- * D12 - RTS RESET
- */
-
- #define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
- extern unsigned short secureedge5410_ioport;
-
- #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
- (secureedge5410_ioport = \
- ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
- #define SECUREEDGE_READ_IOPORT() \
- ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
-#endif
-
-#endif /* _ASM_SH_IO_SNAPGEAR_H */
+++ /dev/null
-#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
-#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
-
-/*
- * linux/include/asm-sh/systemh/7751systemh.h
- *
- * Copyright (C) 2000 Kazumoto Kojima
- *
- * Hitachi SystemH support
-
- * Modified for 7751 SystemH by
- * Jonathan Short, 2002.
- */
-
-/* Box specific addresses. */
-
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_FROM 0x01000000 /* EPROM */
-#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-
-#define PA_EXT4 0x12000000
-#define PA_EXT4_SIZE 0x02000000
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
-
-#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
-#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
-#define PA_LED 0xba000000 /* LED */
-#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
-
-#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
-#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_MODE (PA_MRSHPC + 4)
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define BCR_ILCRA (PA_BCR + 0)
-#define BCR_ILCRB (PA_BCR + 2)
-#define BCR_ILCRC (PA_BCR + 4)
-#define BCR_ILCRD (PA_BCR + 6)
-#define BCR_ILCRE (PA_BCR + 8)
-#define BCR_ILCRF (PA_BCR + 10)
-#define BCR_ILCRG (PA_BCR + 12)
-
-#define IRQ_79C973 13
-
-#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
+++ /dev/null
-/*
- * include/asm-sh/systemh/io.h
- *
- * Stupid I/O definitions for SystemH, cloned from SE7751.
- *
- * Copyright (C) 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_SH_SYSTEMH_IO_H
-#define __ASM_SH_SYSTEMH_IO_H
-
-extern unsigned char sh7751systemh_inb(unsigned long port);
-extern unsigned short sh7751systemh_inw(unsigned long port);
-extern unsigned int sh7751systemh_inl(unsigned long port);
-
-extern void sh7751systemh_outb(unsigned char value, unsigned long port);
-extern void sh7751systemh_outw(unsigned short value, unsigned long port);
-extern void sh7751systemh_outl(unsigned int value, unsigned long port);
-
-extern unsigned char sh7751systemh_inb_p(unsigned long port);
-extern void sh7751systemh_outb_p(unsigned char value, unsigned long port);
-
-extern void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count);
-extern void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count);
-extern void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count);
-extern void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count);
-extern void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count);
-extern void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern unsigned char sh7751systemh_readb(unsigned long addr);
-extern unsigned short sh7751systemh_readw(unsigned long addr);
-extern unsigned int sh7751systemh_readl(unsigned long addr);
-extern void sh7751systemh_writeb(unsigned char b, unsigned long addr);
-extern void sh7751systemh_writew(unsigned short b, unsigned long addr);
-extern void sh7751systemh_writel(unsigned int b, unsigned long addr);
-
-extern unsigned long sh7751systemh_isa_port2addr(unsigned long offset);
-
-#endif /* __ASM_SH_SYSTEMH_IO_H */
-
--- /dev/null
+#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
+#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
+
+/*
+ * linux/include/asm-sh/systemh/7751systemh.h
+ *
+ * Copyright (C) 2000 Kazumoto Kojima
+ *
+ * Hitachi SystemH support
+
+ * Modified for 7751 SystemH by
+ * Jonathan Short, 2002.
+ */
+
+/* Box specific addresses. */
+
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_FROM 0x01000000 /* EPROM */
+#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0x12000000
+#define PA_EXT4_SIZE 0x02000000
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
+#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
+#define PA_LED 0xba000000 /* LED */
+#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE (PA_MRSHPC + 4)
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA (PA_BCR + 0)
+#define BCR_ILCRB (PA_BCR + 2)
+#define BCR_ILCRC (PA_BCR + 4)
+#define BCR_ILCRD (PA_BCR + 6)
+#define BCR_ILCRE (PA_BCR + 8)
+#define BCR_ILCRF (PA_BCR + 10)
+#define BCR_ILCRG (PA_BCR + 12)
+
+#define IRQ_79C973 13
+
+#define __IO_PREFIX sh7751systemh
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff