.ltc = gp100_ltc_new,
.mc = gp100_mc_new,
.mmu = gf100_mmu_new,
+ .secboot = gp102_secboot_new,
+ .sec2 = gp102_sec2_new,
+ .nvdec = gp102_nvdec_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.timer = gk20a_timer_new,
.disp = gp102_disp_new,
.dma = gf119_dma_new,
.fifo = gp100_fifo_new,
+ .gr = gp102_gr_new,
+ .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
.ltc = gp100_ltc_new,
.mc = gp100_mc_new,
.mmu = gf100_mmu_new,
+ .secboot = gp102_secboot_new,
+ .sec2 = gp102_sec2_new,
+ .nvdec = gp102_nvdec_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.timer = gk20a_timer_new,
.disp = gp102_disp_new,
.dma = gf119_dma_new,
.fifo = gp100_fifo_new,
+ .gr = gp102_gr_new,
+ .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
.ltc = gp100_ltc_new,
.mc = gp100_mc_new,
.mmu = gf100_mmu_new,
+ .secboot = gp102_secboot_new,
+ .sec2 = gp102_sec2_new,
+ .nvdec = gp102_nvdec_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.timer = gk20a_timer_new,
.disp = gp102_disp_new,
.dma = gf119_dma_new,
.fifo = gp100_fifo_new,
+ .gr = gp102_gr_new,
+ .sw = gf100_sw_new,
};
static int