MIPS: Add hibernation support

[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
support.  As implemented in this patch cache and tlb flushing will also be
invoked with interrupts disabled so smp_call_function() will blow up in
charming ways.  So limit to !SMP.]

Reviewed-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Yan Hua <yanh@lemote.com>
Reviewed-by: Arnaud Patard <apatard@mandriva.com>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Wu Zhangjin <wuzj@lemote.com>
Signed-off-by: Hu Hongbing <huhb@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cebebf151a143534e17b4d9a8baee2365d3f9db1..b29f0280d71282ad2f2cf142d96e1dc84e0a591a 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2134,6 +2134,10 @@ endmenu
 
 menu "Power management options"
 
+config ARCH_HIBERNATION_POSSIBLE
+       def_bool y
+       depends on !SMP
+
 config ARCH_SUSPEND_POSSIBLE
        def_bool y
        depends on !SMP

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index e5ccc3490d6a2b75e0afc38c22bd70f930fcb8c9..807572a6a4d2df80335ee2334518c9ae5726841f 100644 (file)
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -677,6 +677,9 @@ core-y                      += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
 
 drivers-$(CONFIG_OPROFILE)     += arch/mips/oprofile/
 
+# suspend and hibernation support
+drivers-$(CONFIG_PM)   += arch/mips/power/
+
 ifdef CONFIG_LASAT
 rom.bin rom.sw: vmlinux
        $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@

diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
new file mode 100644 (file)
index 0000000..294cdb6
--- /dev/null
+++ b/arch/mips/include/asm/suspend.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_SUSPEND_H
+#define __ASM_SUSPEND_H
+
+static inline int arch_prepare_suspend(void) { return 0; }
+
+/* References to section boundaries */
+extern const void __nosave_begin, __nosave_end;
+
+#endif /* __ASM_SUSPEND_H */

diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index c901c22d7ad04efb24b4337ef03dec4e30319377..8d006ec656771f3e8735987f7050b62cb5d4e1cd 100644 (file)
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -14,6 +14,7 @@
 #include <linux/mm.h>
 #include <linux/interrupt.h>
 #include <linux/kbuild.h>
+#include <linux/suspend.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 
@@ -326,3 +327,15 @@ void output_octeon_cop2_state_defines(void)
        BLANK();
 }
 #endif
+
+#ifdef CONFIG_HIBERNATION
+void output_pbe_defines(void)
+{
+       COMMENT(" Linux struct pbe offsets. ");
+       OFFSET(PBE_ADDRESS, pbe, address);
+       OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
+       OFFSET(PBE_NEXT, pbe, next);
+       DEFINE(PBE_SIZE, sizeof(struct pbe));
+       BLANK();
+}
+#endif

diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile
new file mode 100644 (file)
index 0000000..73d56b8
--- /dev/null
+++ b/arch/mips/power/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o

diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
new file mode 100644 (file)
index 0000000..7995df4
--- /dev/null
+++ b/arch/mips/power/cpu.c
@@ -0,0 +1,43 @@
+/*
+ * Suspend support specific for mips.
+ *
+ * Licensed under the GPLv2
+ *
+ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Author: Hu Hongbing <huhb@lemote.com>
+ *         Wu Zhangjin <wuzj@lemote.com>
+ */
+#include <asm/suspend.h>
+#include <asm/fpu.h>
+#include <asm/dsp.h>
+
+static u32 saved_status;
+struct pt_regs saved_regs;
+
+void save_processor_state(void)
+{
+       saved_status = read_c0_status();
+
+       if (is_fpu_owner())
+               save_fp(current);
+       if (cpu_has_dsp)
+               save_dsp(current);
+}
+
+void restore_processor_state(void)
+{
+       write_c0_status(saved_status);
+
+       if (is_fpu_owner())
+               restore_fp(current);
+       if (cpu_has_dsp)
+               restore_dsp(current);
+}
+
+int pfn_is_nosave(unsigned long pfn)
+{
+       unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin));
+       unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end));
+
+       return  (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
+}

diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
new file mode 100644 (file)
index 0000000..486bd3f
--- /dev/null
+++ b/arch/mips/power/hibernate.S
@@ -0,0 +1,70 @@
+/*
+ * Hibernation support specific for mips - temporary page tables
+ *
+ * Licensed under the GPLv2
+ *
+ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Author: Hu Hongbing <huhb@lemote.com>
+ *         Wu Zhangjin <wuzj@lemote.com>
+ */
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/asm.h>
+
+.text
+LEAF(swsusp_arch_suspend)
+       PTR_LA t0, saved_regs
+       PTR_S ra, PT_R31(t0)
+       PTR_S sp, PT_R29(t0)
+       PTR_S fp, PT_R30(t0)
+       PTR_S gp, PT_R28(t0)
+       PTR_S s0, PT_R16(t0)
+       PTR_S s1, PT_R17(t0)
+       PTR_S s2, PT_R18(t0)
+       PTR_S s3, PT_R19(t0)
+       PTR_S s4, PT_R20(t0)
+       PTR_S s5, PT_R21(t0)
+       PTR_S s6, PT_R22(t0)
+       PTR_S s7, PT_R23(t0)
+       j swsusp_save
+END(swsusp_arch_suspend)
+
+LEAF(swsusp_arch_resume)
+       PTR_L t0, restore_pblist
+0:
+       PTR_L t1, PBE_ADDRESS(t0)   /* source */
+       PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
+       PTR_ADDIU t3, t1, _PAGE_SIZE
+1:
+       REG_L t8, (t1)
+       REG_S t8, (t2)
+       PTR_ADDIU t1, t1, SZREG
+       PTR_ADDIU t2, t2, SZREG
+       bne t1, t3, 1b
+       PTR_L t0, PBE_NEXT(t0)
+       bnez t0, 0b
+       /* flush caches to make sure context is in memory */
+       PTR_L t0, __flush_cache_all
+       jalr t0
+       /* flush tlb entries */
+#ifdef CONFIG_SMP
+       jal     flush_tlb_all
+#else
+       jal     local_flush_tlb_all
+#endif
+       PTR_LA t0, saved_regs
+       PTR_L ra, PT_R31(t0)
+       PTR_L sp, PT_R29(t0)
+       PTR_L fp, PT_R30(t0)
+       PTR_L gp, PT_R28(t0)
+       PTR_L s0, PT_R16(t0)
+       PTR_L s1, PT_R17(t0)
+       PTR_L s2, PT_R18(t0)
+       PTR_L s3, PT_R19(t0)
+       PTR_L s4, PT_R20(t0)
+       PTR_L s5, PT_R21(t0)
+       PTR_L s6, PT_R22(t0)
+       PTR_L s7, PT_R23(t0)
+       PTR_LI v0, 0x0
+       jr ra
+END(swsusp_arch_resume)