e1000e: cleanup SPACING checkpatch errors and warnings
authorBruce Allan <bruce.w.allan@intel.com>
Wed, 20 Feb 2013 04:05:45 +0000 (04:05 +0000)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Fri, 8 Mar 2013 08:23:56 +0000 (00:23 -0800)
ERROR:SPACING: spaces prohibited around that ':' (ctx:WxV)
ERROR:SPACING: need consistent spacing around '-' (ctx:WxV)
ERROR:SPACING: space required after that ',' (ctx:VxV)
ERROR:SPACING: spaces required around that '=' (ctx:VxV)
WARNING:SPACING: missing space after enum definition

and some similar spacing issues not reported by checkpatch.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/e1000e/82571.c
drivers/net/ethernet/intel/e1000e/ethtool.c
drivers/net/ethernet/intel/e1000e/hw.h
drivers/net/ethernet/intel/e1000e/ich8lan.c
drivers/net/ethernet/intel/e1000e/netdev.c
drivers/net/ethernet/intel/e1000e/phy.c

index e63ddc6d77f420a7ee3201b7a46c2e2112f0435a..2a4ae28e658785404df4498a569db7df4ada3ad2 100644 (file)
@@ -847,7 +847,7 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 
        for (i = 0; i < words; i++) {
                eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
-                       ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
+                       ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
                        E1000_NVM_RW_REG_START);
 
                ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
index fa375dd4da12252e4d5cb69b216210834c634935..bbd4b1b3319d7a4dde7d5814977a5057e45a9e8e 100644 (file)
@@ -39,7 +39,7 @@
 
 #include "e1000.h"
 
-enum {NETDEV_STATS, E1000_STATS};
+enum { NETDEV_STATS, E1000_STATS };
 
 struct e1000_stats {
        char stat_string[ETH_GSTRING_LEN];
index 649bfb67bc05a427eb88987f1415815cd31553fe..84850f7a23e4205650b9cef83f12be762a4feea9 100644 (file)
@@ -167,7 +167,7 @@ enum e1000_1000t_rx_status {
        e1000_1000t_rx_status_undefined = 0xFF
 };
 
-enum e1000_rev_polarity{
+enum e1000_rev_polarity {
        e1000_rev_polarity_normal = 0,
        e1000_rev_polarity_reversed,
        e1000_rev_polarity_undefined = 0xFF
index 37b2003bcc9cc7aaabb4d14255513a52e0d3e57d..705e74f8c1d16b026634e4725f91fd7a89d19e61 100644 (file)
 /* Offset 04h HSFSTS */
 union ich8_hws_flash_status {
        struct ich8_hsfsts {
-               u16 flcdone    :1; /* bit 0 Flash Cycle Done */
-               u16 flcerr     :1; /* bit 1 Flash Cycle Error */
-               u16 dael       :1; /* bit 2 Direct Access error Log */
-               u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
-               u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
-               u16 reserved1  :2; /* bit 13:6 Reserved */
-               u16 reserved2  :6; /* bit 13:6 Reserved */
-               u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
-               u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
+               u16 flcdone:1;  /* bit 0 Flash Cycle Done */
+               u16 flcerr:1;   /* bit 1 Flash Cycle Error */
+               u16 dael:1;     /* bit 2 Direct Access error Log */
+               u16 berasesz:2; /* bit 4:3 Sector Erase Size */
+               u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
+               u16 reserved1:2;        /* bit 13:6 Reserved */
+               u16 reserved2:6;        /* bit 13:6 Reserved */
+               u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
+               u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
        } hsf_status;
        u16 regval;
 };
@@ -78,11 +78,11 @@ union ich8_hws_flash_status {
 /* Offset 06h FLCTL */
 union ich8_hws_flash_ctrl {
        struct ich8_hsflctl {
-               u16 flcgo      :1;   /* 0 Flash Cycle Go */
-               u16 flcycle    :2;   /* 2:1 Flash Cycle */
-               u16 reserved   :5;   /* 7:3 Reserved  */
-               u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
-               u16 flockdn    :6;   /* 15:10 Reserved */
+               u16 flcgo:1;    /* 0 Flash Cycle Go */
+               u16 flcycle:2;  /* 2:1 Flash Cycle */
+               u16 reserved:5; /* 7:3 Reserved  */
+               u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
+               u16 flockdn:6;  /* 15:10 Reserved */
        } hsf_ctrl;
        u16 regval;
 };
@@ -90,10 +90,10 @@ union ich8_hws_flash_ctrl {
 /* ICH Flash Region Access Permissions */
 union ich8_hws_flash_regacc {
        struct ich8_flracc {
-               u32 grra      :8; /* 0:7 GbE region Read Access */
-               u32 grwa      :8; /* 8:15 GbE region Write Access */
-               u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
-               u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
+               u32 grra:8;     /* 0:7 GbE region Read Access */
+               u32 grwa:8;     /* 8:15 GbE region Write Access */
+               u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
+               u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
        } hsf_flregacc;
        u16 regval;
 };
@@ -1773,7 +1773,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
                 * SHRAL/H) and initial CRC values to the MAC
                 */
                for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
-                       u8 mac_addr[ETH_ALEN] = {0};
+                       u8 mac_addr[ETH_ALEN] = { 0 };
                        u32 addr_high, addr_low;
 
                        addr_high = er32(RAH(i));
@@ -2449,8 +2449,8 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 
        ret_val = 0;
        for (i = 0; i < words; i++) {
-               if (dev_spec->shadow_ram[offset+i].modified) {
-                       data[i] = dev_spec->shadow_ram[offset+i].value;
+               if (dev_spec->shadow_ram[offset + i].modified) {
+                       data[i] = dev_spec->shadow_ram[offset + i].value;
                } else {
                        ret_val = e1000_read_flash_word_ich8lan(hw,
                                                                act_offset + i,
@@ -2713,8 +2713,8 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
        nvm->ops.acquire(hw);
 
        for (i = 0; i < words; i++) {
-               dev_spec->shadow_ram[offset+i].modified = true;
-               dev_spec->shadow_ram[offset+i].value = data[i];
+               dev_spec->shadow_ram[offset + i].modified = true;
+               dev_spec->shadow_ram[offset + i].value = data[i];
        }
 
        nvm->ops.release(hw);
@@ -3001,7 +3001,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 
                hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
                /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
-               hsflctl.hsf_ctrl.fldbcount = size -1;
+               hsflctl.hsf_ctrl.fldbcount = size - 1;
                hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
                ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
 
index e8192d3f7eb4c1ba46501fffd782d0a897231291..247f61f77e5df3f9e0d6b98b194966ccbe91d4de 100644 (file)
@@ -1495,7 +1495,7 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
        unsigned int i;
        int cleaned_count = 0;
        bool cleaned = false;
-       unsigned int total_rx_bytes=0, total_rx_packets=0;
+       unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 
        i = rx_ring->next_to_clean;
        rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
@@ -2489,7 +2489,7 @@ static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
        switch (itr_setting) {
        case lowest_latency:
                /* handle TSO and jumbo frames */
-               if (bytes/packets > 8000)
+               if (bytes / packets > 8000)
                        retval = bulk_latency;
                else if ((packets < 5) && (bytes > 512))
                        retval = low_latency;
@@ -2497,13 +2497,13 @@ static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
        case low_latency:  /* 50 usec aka 20000 ints/s */
                if (bytes > 10000) {
                        /* this if handles the TSO accounting */
-                       if (bytes/packets > 8000)
+                       if (bytes / packets > 8000)
                                retval = bulk_latency;
-                       else if ((packets < 10) || ((bytes/packets) > 1200))
+                       else if ((packets < 10) || ((bytes / packets) > 1200))
                                retval = bulk_latency;
                        else if ((packets > 35))
                                retval = lowest_latency;
-               } else if (bytes/packets > 2000) {
+               } else if (bytes / packets > 2000) {
                        retval = bulk_latency;
                } else if (packets <= 2 && bytes < 512) {
                        retval = lowest_latency;
@@ -5346,7 +5346,7 @@ static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
                return 0;
 
        {
-               const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
+               const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
                struct udphdr *udp;
 
                if (ip->protocol != IPPROTO_UDP)
index c39a65e293fa3bb4c04d110c5082b298502773d1..e46b65f11894fb3285e45ee424fcfc01f0311b91 100644 (file)
@@ -1756,7 +1756,7 @@ s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
                if (phy_status & BMSR_LSTATUS)
                        break;
                if (usec_interval >= 1000)
-                       mdelay(usec_interval/1000);
+                       mdelay(usec_interval / 1000);
                else
                        udelay(usec_interval);
        }