KVM: arm64: Fix AArch32 handling of DBGD{CCINT,SCRext} and DBGVCR
authorMarc Zyngier <maz@kernel.org>
Thu, 29 Oct 2020 17:24:09 +0000 (17:24 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 5 Nov 2020 10:07:05 +0000 (11:07 +0100)
commit 4a1c2c7f63c52ccb11770b5ae25920a6b79d3548 upstream.

The DBGD{CCINT,SCRext} and DBGVCR register entries in the cp14 array
are missing their target register, resulting in all accesses being
targetted at the guard sysreg (indexed by __INVALID_SYSREG__).

Point the emulation code at the actual register entries.

Fixes: bdfb4b389c8d ("arm64: KVM: add trap handlers for AArch32 debug registers")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201029172409.2768336-1-maz@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm64/include/asm/kvm_host.h
arch/arm64/kvm/sys_regs.c

index 87615facf9596162c07fc81886009ac2f20b0c71..02d34caa7bffcea5617264394d2a59c2c9a46c07 100644 (file)
@@ -185,6 +185,7 @@ enum vcpu_sysreg {
 #define cp14_DBGWCR0   (DBGWCR0_EL1 * 2)
 #define cp14_DBGWVR0   (DBGWVR0_EL1 * 2)
 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
+#define cp14_DBGVCR    (DBGVCR32_EL2 * 2)
 
 #define NR_COPRO_REGS  (NR_SYS_REGS * 2)
 
index 32ae5c9daac40485a1edd76574ea810b73f0deee..1ee4d9216841ecb07d09786467f05a4c2a5648bf 100644 (file)
@@ -1178,9 +1178,9 @@ static const struct sys_reg_desc cp14_regs[] = {
        { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
        DBG_BCR_BVR_WCR_WVR(1),
        /* DBGDCCINT */
-       { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
+       { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
        /* DBGDSCRext */
-       { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
+       { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
        DBG_BCR_BVR_WCR_WVR(2),
        /* DBGDTR[RT]Xint */
        { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
@@ -1195,7 +1195,7 @@ static const struct sys_reg_desc cp14_regs[] = {
        { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
        DBG_BCR_BVR_WCR_WVR(6),
        /* DBGVCR */
-       { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
+       { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
        DBG_BCR_BVR_WCR_WVR(7),
        DBG_BCR_BVR_WCR_WVR(8),
        DBG_BCR_BVR_WCR_WVR(9),