for (i = 0; i < dm_timer_count; i++) {
u32 l;
- l = omap_dm_timer_read_reg(&dm_timers[n], OMAP_TIMER_CTRL_REG);
+ l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
if (l & OMAP_TIMER_CTRL_ST) {
if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
inputmask &= ~(1 << 1);
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
+#include <asm/arch/dmtimer.h>
struct sys_timer omap_timer;
#elif defined(CONFIG_ARCH_OMAP2)
-#include <asm/arch/dmtimer.h>
-
static struct omap_dm_timer *gptimer;
static inline void omap_32k_timer_start(unsigned long load_val)
omap_timer.offset = omap_32k_timer_gettimeoffset;
omap_32k_last_tick = omap_32k_sync_timer_read();
+#ifdef CONFIG_ARCH_OMAP2
/* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
if (cpu_is_omap24xx()) {
gptimer = omap_dm_timer_request_specific(1);
OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
OMAP_TIMER_INT_MATCH);
}
+#endif
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
}