ARM: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs

UART modules can use DMA for offloading data transfers and reducing
interrupts, so enable this feature for Exynos5 boards. Tested on
Google ChromeBook Snow (Exynos5250), Odroid XU (Exynos5410) and Odroid
XU3 (Exynos5422) boards.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b6d7444d85858e6ab16ef59deaf763e60b95370d..0e04460a815a028859474c15bc3ed294fc8bb3a4 100644 (file)
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -1043,21 +1043,29 @@
 &serial_0 {
        clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma0 13>, <&pdma0 14>;
+       dma-names = "rx", "tx";
 };
 
 &serial_1 {
        clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma1 15>, <&pdma1 16>;
+       dma-names = "rx", "tx";
 };
 
 &serial_2 {
        clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma0 15>, <&pdma0 16>;
+       dma-names = "rx", "tx";
 };
 
 &serial_3 {
        clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma1 17>, <&pdma1 18>;
+       dma-names = "rx", "tx";
 };
 
 #include "exynos5250-pinctrl.dtsi"

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 2b6adafe18e23a1cdc87eab93d08d77181aee231..7eab4bc07cec6cde6b645823040ea708d1936dad 100644 (file)
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -340,21 +340,29 @@
 &serial_0 {
        clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma0 13>, <&pdma0 14>;
+       dma-names = "rx", "tx";
 };
 
 &serial_1 {
        clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma1 15>, <&pdma1 16>;
+       dma-names = "rx", "tx";
 };
 
 &serial_2 {
        clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma0 15>, <&pdma0 16>;
+       dma-names = "rx", "tx";
 };
 
 &serial_3 {
        clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma1 17>, <&pdma1 18>;
+       dma-names = "rx", "tx";
 };
 
 &sss {

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 906a1a42a7ea4e9a41d60f89ff8701cc10f44872..0154c2e373f83018265a59e19bf0748c3feb3e1c 100644 (file)
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1406,21 +1406,29 @@
 &serial_0 {
        clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma0 13>, <&pdma0 14>;
+       dma-names = "rx", "tx";
 };
 
 &serial_1 {
        clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma1 15>, <&pdma1 16>;
+       dma-names = "rx", "tx";
 };
 
 &serial_2 {
        clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma0 15>, <&pdma0 16>;
+       dma-names = "rx", "tx";
 };
 
 &serial_3 {
        clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
        clock-names = "uart", "clk_uart_baud0";
+       dmas = <&pdma1 17>, <&pdma1 18>;
+       dma-names = "rx", "tx";
 };
 
 &sss {