#include <asm/io.h>
#include <asm/irq.h>
-#define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \
- ((cpu) * REALVIEW_TWD_SIZE))
+#define TWD_BASE(cpu) (__io_address(REALVIEW_EB11MP_TWD_BASE) + \
+ ((cpu) * REALVIEW_EB11MP_TWD_SIZE))
static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
{
unsigned int ncores;
- ncores = __raw_readl(__io_address(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG);
+ ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG);
return (ncores & 0x03) + 1;
}
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
- gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
+ gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
/*
* let the primary processor know we're out of the
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>
+#include <asm/arch/board-eb.h>
#include <asm/arch/irqs.h>
#include "core.h"
--- /dev/null
+/*
+ * include/asm-arm/arch-realview/board-eb.h
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_EB_H
+#define __ASM_ARCH_BOARD_EB_H
+
+#include <asm/arch/platform.h>
+
+/*
+ * RealView EB + ARM11MPCore peripheral addresses
+ */
+#ifdef CONFIG_REALVIEW_MPCORE_REVB
+#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
+#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB11MP_TWD_BASE 0x10100700
+#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
+#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
+#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
+#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
+#else
+#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
+#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB11MP_TWD_BASE 0x1F000700
+#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
+#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
+#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
+#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
+#endif
+
+#define IRQ_EB_GIC_START 32
+
+/*
+ * RealView EB interrupt sources
+ */
+#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
+#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
+#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
+#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
+#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
+#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
+#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
+#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
+#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
+ /* 9 reserved */
+#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
+#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
+#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
+#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
+#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
+#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
+#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
+#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
+#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
+#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
+#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
+#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
+#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
+#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
+#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
+#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
+#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
+#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
+#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
+#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
+#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
+#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
+
+/*
+ * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
+ */
+#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
+#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
+#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
+#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
+#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
+#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
+#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
+#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
+#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
+#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
+#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
+#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
+#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
+#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
+#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
+#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
+
+#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
+#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
+#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
+#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
+#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
+#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
+#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
+#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
+#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
+#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
+#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
+#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
+
+#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
+#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
+#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
+
+#define IRQ_EB11MP_UART2 -1
+#define IRQ_EB11MP_UART3 -1
+#define IRQ_EB11MP_CLCD -1
+#define IRQ_EB11MP_DMA -1
+#define IRQ_EB11MP_WDOG -1
+#define IRQ_EB11MP_GPIO0 -1
+#define IRQ_EB11MP_GPIO1 -1
+#define IRQ_EB11MP_GPIO2 -1
+#define IRQ_EB11MP_SCI -1
+#define IRQ_EB11MP_SSP -1
+
+#define NR_GIC_EB11MP 2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_EB
+ */
+#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_EB) \
+ && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
+#undef NR_IRQS
+#define NR_IRQS NR_IRQS_EB
+#endif
+
+#if defined(CONFIG_REALVIEW_MPCORE) \
+ && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
+#undef MAX_GIC_NR
+#define MAX_GIC_NR NR_GIC_EB11MP
+#endif
+
+#endif /* __ASM_ARCH_BOARD_EB_H */
*/
#include <asm/hardware.h>
#include <asm/hardware/gic.h>
+#include <asm/arch/board-eb.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
+#ifdef CONFIG_REALVIEW_MPCORE
+ ldr \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE)
+#else
ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
+#endif
.endm
.macro arch_ret_to_user, tmp1, tmp2
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
-#include <asm/arch/platform.h>
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include <asm/arch/platform.h>
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
-#define IRQ_LOCALTIMER 29
-#define IRQ_LOCALWDOG 30
+#include <asm/arch/board-eb.h>
-/*
- * IRQ interrupts definitions are the same the INT definitions
- * held within platform.h
- */
-#define IRQ_GIC_START 32
-#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
-#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
-#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
-#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
-#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
-#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
-#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
-#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
-#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
-#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
-#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
-#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
-#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
-#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
-#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
-#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
-#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
-#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
-#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
-#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
-#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
-#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
-#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
-#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
-#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
-#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
-#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
-#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
-#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
-#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
-#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
-#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
-#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
-#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
-#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
-#define IRQ_USB (IRQ_GIC_START + INT_USB)
-#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0)
-#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1)
-#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2)
-#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3)
-#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0)
-#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1)
-#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2)
-#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3)
-#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4)
-#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5)
-#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
-#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
-#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1)
-#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
+#define IRQ_GIC_START 32
-#define IRQMASK_WDOGINT INTMASK_WDOGINT
-#define IRQMASK_SOFTINT INTMASK_SOFTINT
-#define IRQMASK_COMMRx INTMASK_COMMRx
-#define IRQMASK_COMMTx INTMASK_COMMTx
-#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
-#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
-#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
-#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
-#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
-#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
-#define IRQMASK_RTCINT INTMASK_RTCINT
-#define IRQMASK_SSPINT INTMASK_SSPINT
-#define IRQMASK_UARTINT0 INTMASK_UARTINT0
-#define IRQMASK_UARTINT1 INTMASK_UARTINT1
-#define IRQMASK_UARTINT2 INTMASK_UARTINT2
-#define IRQMASK_SCIINT INTMASK_SCIINT
-#define IRQMASK_CLCDINT INTMASK_CLCDINT
-#define IRQMASK_DMAINT INTMASK_DMAINT
-#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
-#define IRQMASK_MBXINT INTMASK_MBXINT
-#define IRQMASK_GNDINT INTMASK_GNDINT
-#define IRQMASK_MMCI0B INTMASK_MMCI0B
-#define IRQMASK_MMCI1B INTMASK_MMCI1B
-#define IRQMASK_KMI0 INTMASK_KMI0
-#define IRQMASK_KMI1 INTMASK_KMI1
-#define IRQMASK_SCI3 INTMASK_SCI3
-#define IRQMASK_UART3 INTMASK_UART3
-#define IRQMASK_CLCD INTMASK_CLCD
-#define IRQMASK_TOUCH INTMASK_TOUCH
-#define IRQMASK_KEYPAD INTMASK_KEYPAD
-#define IRQMASK_DoC INTMASK_DoC
-#define IRQMASK_MMCI0A INTMASK_MMCI0A
-#define IRQMASK_MMCI1A INTMASK_MMCI1A
-#define IRQMASK_AACI INTMASK_AACI
-#define IRQMASK_ETH INTMASK_ETH
-#define IRQMASK_USB INTMASK_USB
+#ifndef NR_IRQS
+#error "NR_IRQS not defined by the board-specific files"
+#endif
-#define NR_IRQS (IRQ_GIC_START + 96)
+#endif
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#ifndef __address_h
-#define __address_h 1
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
/*
* Memory definitions
#define REALVIEW_SYS_24MHz_OFFSET 0x5C
#define REALVIEW_SYS_MISC_OFFSET 0x60
#define REALVIEW_SYS_IOSEL_OFFSET 0x70
-#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80
-#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84
-#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88
-#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C
-#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90
+#define REALVIEW_SYS_PROCID_OFFSET 0x84
+#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
+#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
+#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
+#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
+#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
#define REALVIEW_SYS_BASE 0x10000000
#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
+#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
/* Reserved 0x1001A000 - 0x1001FFFF */
#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
-#ifndef CONFIG_REALVIEW_MPCORE
#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
-#else
-#ifdef CONFIG_REALVIEW_MPCORE_REVB
-#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
-#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
-#define REALVIEW_TWD_BASE 0x10100700
-#define REALVIEW_TWD_SIZE 0x00000100
-#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
-#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
-#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
-#else
-#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
-#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
-#define REALVIEW_TWD_BASE 0x1F000700
-#define REALVIEW_TWD_SIZE 0x00000100
-#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
-#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
-#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
-#endif
-#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
-#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
-#endif
#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
/* Reserved 0x10090000 - 0x100EFFFF */
#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
-/* ------------------------------------------------------------------------
- * Interrupts - bit assignment (primary)
- * ------------------------------------------------------------------------
- */
-#ifndef CONFIG_REALVIEW_MPCORE
-#define INT_WDOGINT 0 /* Watchdog timer */
-#define INT_SOFTINT 1 /* Software interrupt */
-#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
-#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
-#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
-#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
-#define INT_GPIOINT0 6 /* GPIO 0 */
-#define INT_GPIOINT1 7 /* GPIO 1 */
-#define INT_GPIOINT2 8 /* GPIO 2 */
-/* 9 reserved */
-#define INT_RTCINT 10 /* Real Time Clock */
-#define INT_SSPINT 11 /* Synchronous Serial Port */
-#define INT_UARTINT0 12 /* UART 0 on development chip */
-#define INT_UARTINT1 13 /* UART 1 on development chip */
-#define INT_UARTINT2 14 /* UART 2 on development chip */
-#define INT_UARTINT3 15 /* UART 3 on development chip */
-#define INT_SCIINT 16 /* Smart Card Interface */
-#define INT_MMCI0A 17 /* Multimedia Card 0A */
-#define INT_MMCI0B 18 /* Multimedia Card 0B */
-#define INT_AACI 19 /* Audio Codec */
-#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
-#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
-#define INT_CHARLCD 22 /* Character LCD */
-#define INT_CLCDINT 23 /* CLCD controller */
-#define INT_DMAINT 24 /* DMA controller */
-#define INT_PWRFAILINT 25 /* Power failure */
-#define INT_PISMO 26
-#define INT_DoC 27 /* Disk on Chip memory controller */
-#define INT_ETH 28 /* Ethernet controller */
-#define INT_USB 29 /* USB controller */
-#define INT_TSPENINT 30 /* Touchscreen pen */
-#define INT_TSKPADINT 31 /* Touchscreen keypad */
-
-#else
-
-#define MAX_GIC_NR 2
-
-#define INT_AACI 0
-#define INT_TIMERINT0_1 1
-#define INT_TIMERINT2_3 2
-#define INT_USB 3
-#define INT_UARTINT0 4
-#define INT_UARTINT1 5
-#define INT_RTCINT 6
-#define INT_KMI0 7
-#define INT_KMI1 8
-#define INT_ETH 9
-#define INT_EB_IRQ1 10 /* main GIC */
-#define INT_EB_IRQ2 11 /* tile GIC */
-#define INT_EB_FIQ1 12 /* main GIC */
-#define INT_EB_FIQ2 13 /* tile GIC */
-#define INT_MMCI0A 14
-#define INT_MMCI0B 15
-
-#define INT_PMU_CPU0 17
-#define INT_PMU_CPU1 18
-#define INT_PMU_CPU2 19
-#define INT_PMU_CPU3 20
-#define INT_PMU_SCU0 21
-#define INT_PMU_SCU1 22
-#define INT_PMU_SCU2 23
-#define INT_PMU_SCU3 24
-#define INT_PMU_SCU4 25
-#define INT_PMU_SCU5 26
-#define INT_PMU_SCU6 27
-#define INT_PMU_SCU7 28
-
-#define INT_L220_EVENT 29
-#define INT_L220_SLAVE 30
-#define INT_L220_DECODE 31
-
-#define INT_UARTINT2 -1
-#define INT_UARTINT3 -1
-#define INT_CLCDINT -1
-#define INT_DMAINT -1
-#define INT_WDOGINT -1
-#define INT_GPIOINT0 -1
-#define INT_GPIOINT1 -1
-#define INT_GPIOINT2 -1
-#define INT_SCIINT -1
-#define INT_SSPINT -1
-#endif
-
-/*
- * Interrupt bit positions
- *
- */
-#define INTMASK_WDOGINT (1 << INT_WDOGINT)
-#define INTMASK_SOFTINT (1 << INT_SOFTINT)
-#define INTMASK_COMMRx (1 << INT_COMMRx)
-#define INTMASK_COMMTx (1 << INT_COMMTx)
-#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
-#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
-#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
-#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
-#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
-#define INTMASK_RTCINT (1 << INT_RTCINT)
-#define INTMASK_SSPINT (1 << INT_SSPINT)
-#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
-#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
-#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
-#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
-#define INTMASK_SCIINT (1 << INT_SCIINT)
-#define INTMASK_MMCI0A (1 << INT_MMCI0A)
-#define INTMASK_MMCI0B (1 << INT_MMCI0B)
-#define INTMASK_AACI (1 << INT_AACI)
-#define INTMASK_KMI0 (1 << INT_KMI0)
-#define INTMASK_KMI1 (1 << INT_KMI1)
-#define INTMASK_CHARLCD (1 << INT_CHARLCD)
-#define INTMASK_CLCDINT (1 << INT_CLCDINT)
-#define INTMASK_DMAINT (1 << INT_DMAINT)
-#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
-#define INTMASK_PISMO (1 << INT_PISMO)
-#define INTMASK_DoC (1 << INT_DoC)
-#define INTMASK_ETH (1 << INT_ETH)
-#define INTMASK_USB (1 << INT_USB)
-#define INTMASK_TSPENINT (1 << INT_TSPENINT)
-#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
-
-#define MAXIRQNUM 31
-#define MAXFIQNUM 31
-#define MAXSWINUM 31
-
/*
* Application Flash
*
#define REALVIEW_CSR_BASE 0x10000000
#define REALVIEW_CSR_SIZE 0x10000000
-#endif
-
-/* END */
+#endif /* __ASM_ARCH_PLATFORM_H */
#ifndef __ASMARM_ARCH_SCU_H
#define __ASMARM_ARCH_SCU_H
-#include <asm/arch/platform.h>
+#include <asm/arch/board-eb.h>
-#define SCU_BASE REALVIEW_MPCORE_SCU_BASE
+#define SCU_BASE REALVIEW_EB11MP_SCU_BASE
#endif
*/
#include <asm/hardware.h>
+#include <asm/arch/platform.h>
+
#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff