drm/radeon: add get_allowed_info_register for CIK
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Oct 2014 15:18:46 +0000 (11:18 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Mar 2015 16:26:41 +0000 (12:26 -0400)
Registers that can be fetched from the info ioctl.

Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cik.c
drivers/gpu/drm/radeon/cikd.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h

index 3e670d344a2047151e289ab7dce348001ddf4280..e1db25e48688ff3e7445b5065b95ee8ee12b3d83 100644 (file)
@@ -141,6 +141,39 @@ static void cik_fini_cg(struct radeon_device *rdev);
 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
                                          bool enable);
 
+/**
+ * cik_get_allowed_info_register - fetch the register for the info ioctl
+ *
+ * @rdev: radeon_device pointer
+ * @reg: register offset in bytes
+ * @val: register value
+ *
+ * Returns 0 for success or -EINVAL for an invalid register
+ *
+ */
+int cik_get_allowed_info_register(struct radeon_device *rdev,
+                                 u32 reg, u32 *val)
+{
+       switch (reg) {
+       case GRBM_STATUS:
+       case GRBM_STATUS2:
+       case GRBM_STATUS_SE0:
+       case GRBM_STATUS_SE1:
+       case GRBM_STATUS_SE2:
+       case GRBM_STATUS_SE3:
+       case SRBM_STATUS:
+       case SRBM_STATUS2:
+       case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
+       case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):
+       case UVD_STATUS:
+       /* TODO VCE */
+               *val = RREG32(reg);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 /* get temperature in millidegrees */
 int ci_get_temp(struct radeon_device *rdev)
 {
index c648e1996dabac449dfb838e018cad85b2d3bb61..4870df898230cb3c4f02f160be9cf024e8a003ac 100644 (file)
 #      define CLK_OD(x)                                ((x) << 6)
 #      define CLK_OD_MASK                              (0x1f << 6)
 
+#define UVD_STATUS                                     0xf6bc
+
 /* UVD clocks */
 
 #define CG_DCLK_CNTL                   0xC050009C
index 21e5fe64f3621d8b75cfa74fae870f82fe9209cb..fafd8ce4d58fc6a844b9615aa3b013cf793123c6 100644 (file)
@@ -2075,6 +2075,7 @@ static struct radeon_asic ci_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &cik_get_xclk,
        .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
+       .get_allowed_info_register = cik_get_allowed_info_register,
        .gart = {
                .tlb_flush = &cik_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
@@ -2187,6 +2188,7 @@ static struct radeon_asic kv_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &cik_get_xclk,
        .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
+       .get_allowed_info_register = cik_get_allowed_info_register,
        .gart = {
                .tlb_flush = &cik_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
index f650bff863cdbde37dce05884a368d59dadfac2f..cf0a90bb61cab3a7bce074a931440a3d12cfa115 100644 (file)
@@ -865,6 +865,8 @@ void cik_sdma_set_wptr(struct radeon_device *rdev,
                       struct radeon_ring *ring);
 int ci_get_temp(struct radeon_device *rdev);
 int kv_get_temp(struct radeon_device *rdev);
+int cik_get_allowed_info_register(struct radeon_device *rdev,
+                                 u32 reg, u32 *val);
 
 int ci_dpm_init(struct radeon_device *rdev);
 int ci_dpm_enable(struct radeon_device *rdev);